riscv/rocket-chip
1
0 Fork 0
Code Releases Activity

Bump Chisel and FIRRTL for annotations refactor (#1261)

Browse Source 
Also brings in an autoclonetype enhancement and some bug fixes
This commit is contained in:
Jack Koenig authored and Henry Cook committed 2018-03-07 10:22:38 -08:00
1 parent d0b46c5b8f
commit 64b707cbb6
7 files changed
+9 -17
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

src/main/scala/devices/debug/Debug.scala
+1 -1
View File
@@ -938,7 +938,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
//------------------------
// DMI Register Control and Status
abstractCommandBusy := (ctrlStateReg != CtrlState(Waiting))
abstractCommandBusy := (ctrlStateReg =/= CtrlState(Waiting))
ABSTRACTCSWrEnLegal := (ctrlStateReg === CtrlState(Waiting))
COMMANDWrEnLegal := (ctrlStateReg === CtrlState(Waiting))