From 64b707cbb6b4b83acae4f59f249d0a0b5c382ba1 Mon Sep 17 00:00:00 2001
From: Jack Koenig <jack.koenig3@gmail.com>
Date: Wed, 7 Mar 2018 13:22:38 -0500
Subject: [PATCH] Bump Chisel and FIRRTL for annotations refactor (#1261)

Also brings in an autoclonetype enhancement and some bug fixes
---
 chisel3                                  | 2 +-
 emulator/Makefrag-verilator              | 2 +-
 firrtl                                   | 2 +-
 src/main/scala/devices/debug/Debug.scala | 2 +-
 src/main/scala/util/GeneratorUtils.scala | 7 +++----
 src/main/scala/util/Misc.scala           | 9 +--------
 vsim/Makefrag-verilog                    | 2 +-
 7 files changed, 9 insertions(+), 17 deletions(-)

diff --git a/chisel3 b/chisel3
index 97871178..531dd6cb 160000
--- a/chisel3
+++ b/chisel3
@@ -1 +1 @@
-Subproject commit 97871178cb511063965f971b768f91c289c4776f
+Subproject commit 531dd6cb7a91b9bb642368d792e9c5e0c1c72089
diff --git a/emulator/Makefrag-verilator b/emulator/Makefrag-verilator
index 9e39574c..99763f5b 100644
--- a/emulator/Makefrag-verilator
+++ b/emulator/Makefrag-verilator
@@ -14,7 +14,7 @@ $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(boot
 
 %.v %.conf: %.fir $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
-	$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$*.conf -faf $*.anno
+	$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$*.conf -faf $*.anno.json
 
 $(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(VLSI_MEM_GEN)
 	cd $(generated_dir) && \
diff --git a/firrtl b/firrtl
index b90fc784..6ebd1585 160000
--- a/firrtl
+++ b/firrtl
@@ -1 +1 @@
-Subproject commit b90fc784a1819c1d7905910130a7da022214bc22
+Subproject commit 6ebd1585e891d0d31cd99ef3e63038b0675cf8f9
diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala
index a44c930e..03b43ed8 100644
--- a/src/main/scala/devices/debug/Debug.scala
+++ b/src/main/scala/devices/debug/Debug.scala
@@ -938,7 +938,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
     //------------------------
     // DMI Register Control and Status
 
-    abstractCommandBusy := (ctrlStateReg != CtrlState(Waiting))
+    abstractCommandBusy := (ctrlStateReg =/= CtrlState(Waiting))
 
     ABSTRACTCSWrEnLegal   := (ctrlStateReg === CtrlState(Waiting))
     COMMANDWrEnLegal      := (ctrlStateReg === CtrlState(Waiting))
diff --git a/src/main/scala/util/GeneratorUtils.scala b/src/main/scala/util/GeneratorUtils.scala
index 4a151cd3..ba2ad484 100644
--- a/src/main/scala/util/GeneratorUtils.scala
+++ b/src/main/scala/util/GeneratorUtils.scala
@@ -10,8 +10,7 @@ import freechips.rocketchip.system.{TestGeneration, DefaultTestSuites}
 import freechips.rocketchip.config._
 import freechips.rocketchip.diplomacy.LazyModule
 import java.io.{File, FileWriter}
-import net.jcazevedo.moultingyaml._
-import firrtl.annotations.AnnotationYamlProtocol._
+import firrtl.annotations.JsonProtocol
 
 /** Representation of the information this Generator needs to collect from external sources. */
 case class ParsedInputNames(
@@ -99,9 +98,9 @@ trait GeneratorApp extends App with HasGeneratorUtilities {
   }
 
   def generateAnno {
-    val annotationFile = new File(td, s"$longName.anno")
+    val annotationFile = new File(td, s"$longName.anno.json")
     val af = new FileWriter(annotationFile)
-    af.write(circuit.annotations.toArray.toYaml.prettyPrint)
+    af.write(JsonProtocol.serialize(circuit.annotations.map(_.toFirrtl)))
     af.close()
   }
 
diff --git a/src/main/scala/util/Misc.scala b/src/main/scala/util/Misc.scala
index 163a3013..eabfa3af 100644
--- a/src/main/scala/util/Misc.scala
+++ b/src/main/scala/util/Misc.scala
@@ -4,7 +4,7 @@
 package freechips.rocketchip.util
 
 import Chisel._
-import chisel3.experimental.{ChiselAnnotation, RawModule}
+import chisel3.experimental.{dontTouch, RawModule}
 import freechips.rocketchip.config.Parameters
 import scala.math._
 
@@ -14,13 +14,6 @@ class ParameterizedBundle(implicit p: Parameters) extends Bundle
 trait DontTouch {
   self: RawModule =>
 
-  def dontTouch(data: Data): Unit = data match {
-    case agg: Aggregate =>
-      agg.getElements.foreach(dontTouch)
-    case elt: Element =>
-      annotate(ChiselAnnotation(elt, classOf[firrtl.Transform], "DONTtouch!"))
-  }
-
   /** Marks every port as don't touch
     *
     * @note This method can only be called after the Module has been fully constructed
diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog
index fb1e70fd..82db9f7a 100644
--- a/vsim/Makefrag-verilog
+++ b/vsim/Makefrag-verilog
@@ -14,7 +14,7 @@ $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(boot
 
 $(generated_dir)/%.v $(generated_dir)/%.conf: $(generated_dir)/%.fir $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
-	$(FIRRTL) -i $< -o $(generated_dir)/$*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$*.conf -faf $(generated_dir)/$*.anno
+	$(FIRRTL) -i $< -o $(generated_dir)/$*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$*.conf -faf $(generated_dir)/$*.anno.json
 
 $(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen)
 	cd $(generated_dir) && \