riscv/rocket-chip
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selectively enable or disable uncached and cached generators

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This commit is contained in:
Howard Mao 2015-10-31 17:43:25 -07:00
parent bcc631f756
commit 644b66a3a8
2 changed files with 41 additions and 20 deletions
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4
groundtest/src/main/scala/generator.scala
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@ -9,12 +9,16 @@ import cde.{Parameters, Field}
case object NGeneratorsPerTile extends Field[Int] case object NGeneratorsPerTile extends Field[Int]
case object NGeneratorTiles extends Field[Int] case object NGeneratorTiles extends Field[Int]
case object GenerateUncached extends Field[Boolean]
case object GenerateCached extends Field[Boolean]
trait HasGeneratorParams { trait HasGeneratorParams {
implicit val p: Parameters implicit val p: Parameters
val nGensPerTile = p(NGeneratorsPerTile) val nGensPerTile = p(NGeneratorsPerTile)
val nGenTiles = p(NGeneratorTiles) val nGenTiles = p(NGeneratorTiles)
val nGens = nGensPerTile * nGenTiles val nGens = nGensPerTile * nGenTiles
val genUncached = p(GenerateUncached)
val genCached = p(GenerateCached)
} }
class UncachedTileLinkGenerator(id: Int) class UncachedTileLinkGenerator(id: Int)

25
groundtest/src/main/scala/tile.scala
View File

@ -39,19 +39,33 @@ class GeneratorTile(id: Int, resetSignal: Bool)
val gen_finished = Wire(Vec(2 * nGensPerTile, Bool())) val gen_finished = Wire(Vec(2 * nGensPerTile, Bool()))
if (genUncached) {
val uncacheArb = Module(new ClientUncachedTileLinkIOArbiter(nGensPerTile)) val uncacheArb = Module(new ClientUncachedTileLinkIOArbiter(nGensPerTile))
for (i <- 0 until nGensPerTile) {
val genid = id * nGensPerTile + i
val uncacheGen = Module(new UncachedTileLinkGenerator(genid))
uncacheArb.io.in(i) <> uncacheGen.io.mem
gen_finished(2 * i) := uncacheGen.io.finished
}
io.uncached(0) <> uncacheArb.io.out
} else {
io.uncached(0).acquire.valid := Bool(false)
io.uncached(0).grant.ready := Bool(false)
for (i <- 0 until nGensPerTile) { gen_finished(2 * i) := Bool(false) }
}
if (genCached) {
val cacheArb = Module(new HellaCacheArbiter(nGensPerTile)(dcacheParams)) val cacheArb = Module(new HellaCacheArbiter(nGensPerTile)(dcacheParams))
val cache = Module(new HellaCache()(dcacheParams)) val cache = Module(new HellaCache()(dcacheParams))
for (i <- 0 until nGensPerTile) { for (i <- 0 until nGensPerTile) {
val genid = id * nGensPerTile + i val genid = id * nGensPerTile + i
val uncacheGen = Module(new UncachedTileLinkGenerator(genid))
val cacheGen = Module(new HellaCacheGenerator(genid)(dcacheParams)) val cacheGen = Module(new HellaCacheGenerator(genid)(dcacheParams))
val cacheIF = Module(new SimpleHellaCacheIF()(dcacheParams)) val cacheIF = Module(new SimpleHellaCacheIF()(dcacheParams))
uncacheArb.io.in(i) <> uncacheGen.io.mem
cacheIF.io.requestor <> cacheGen.io.mem cacheIF.io.requestor <> cacheGen.io.mem
cacheArb.io.requestor(i) <> cacheIF.io.cache cacheArb.io.requestor(i) <> cacheIF.io.cache
gen_finished(2 * i) := uncacheGen.io.finished
gen_finished(2 * i + 1) := cacheGen.io.finished gen_finished(2 * i + 1) := cacheGen.io.finished
} }
@ -62,8 +76,11 @@ class GeneratorTile(id: Int, resetSignal: Bool)
assert(!cache.io.ptw.req.valid, assert(!cache.io.ptw.req.valid,
"Cache should not be using virtual addressing") "Cache should not be using virtual addressing")
io.uncached(0) <> uncacheArb.io.out
io.cached(0) <> cache.io.mem io.cached(0) <> cache.io.mem
} else {
io.cached(0) <> Module(new DummyCache).io
for (i <- 0 until nGensPerTile) { gen_finished(2 * i + 1) := Bool(true) }
}
val all_done = gen_finished.reduce(_ && _) val all_done = gen_finished.reduce(_ && _)