riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

periphery: peripheryBusBytes and socBusBytes

Browse Source
This commit is contained in:
Henry Cook 2017-02-27 19:19:41 -08:00 committed by GitHub
parent 35877e6ec1
commit 62f5727bc6
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/rocketchip/Periphery.scala
View File

@ -38,7 +38,9 @@ case object ZeroConfig extends Field[ZeroConfig]
trait HasPeripheryParameters { trait HasPeripheryParameters {
implicit val p: Parameters implicit val p: Parameters
def peripheryBusConfig = p(PeripheryBusConfig) def peripheryBusConfig = p(PeripheryBusConfig)
def peripheryBusBytes = peripheryBusConfig.beatBytes
def socBusConfig = p(SOCBusConfig) def socBusConfig = p(SOCBusConfig)
def socBusBytes = socBusConfig.beatBytes
def cacheBlockBytes = p(CacheBlockBytes) def cacheBlockBytes = p(CacheBlockBytes)
def peripheryBusArithmetic = p(PeripheryBusArithmetic) def peripheryBusArithmetic = p(PeripheryBusArithmetic)
def nMemoryChannels = p(coreplex.BankedL2Config).nMemoryChannels def nMemoryChannels = p(coreplex.BankedL2Config).nMemoryChannels