From 62f5727bc677b4986b6a3d3f33111fb2cf5645c9 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Mon, 27 Feb 2017 19:19:41 -0800
Subject: [PATCH] periphery: peripheryBusBytes and socBusBytes

---
 src/main/scala/rocketchip/Periphery.scala | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala
index e495ef33..d8d4aae5 100644
--- a/src/main/scala/rocketchip/Periphery.scala
+++ b/src/main/scala/rocketchip/Periphery.scala
@@ -38,7 +38,9 @@ case object ZeroConfig extends Field[ZeroConfig]
 trait HasPeripheryParameters {
   implicit val p: Parameters
   def peripheryBusConfig = p(PeripheryBusConfig)
+  def peripheryBusBytes = peripheryBusConfig.beatBytes
   def socBusConfig = p(SOCBusConfig)
+  def socBusBytes = socBusConfig.beatBytes
   def cacheBlockBytes = p(CacheBlockBytes)
   def peripheryBusArithmetic = p(PeripheryBusArithmetic)
   def nMemoryChannels = p(coreplex.BankedL2Config).nMemoryChannels