riscv/rocket-chip
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Perform tag error detectoin/correction in same cycle as RAM

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The tag RAMs tend to be fast, so take up some of the slack.
This makes s2_nack faster.
This commit is contained in:
Andrew Waterman 2017-08-08 10:21:30 -07:00
parent 6d1d285464
commit 62ccba304c
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/rocket/DCache.scala
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@ -207,9 +207,9 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val s2_write = isWrite(s2_req.cmd) val s2_write = isWrite(s2_req.cmd)
val s2_readwrite = s2_read || s2_write val s2_readwrite = s2_read || s2_write
val s2_flush_valid_pre_tag_ecc = RegNext(s1_flush_valid) val s2_flush_valid_pre_tag_ecc = RegNext(s1_flush_valid)
val s2_meta = s1_meta.map(RegEnable(_, s1_valid_not_nacked || s1_flush_valid || s1_probe)).map(tECC.decode(_)) val s1_meta_decoded = s1_meta.map(tECC.decode(_))
val s2_meta_corrected = s2_meta.map(_.corrected.asTypeOf(new L1Metadata)) val s2_meta_errors = s1_meta_decoded.map(m => RegEnable(m.error, s1_valid_not_nacked || s1_flush_valid || s1_probe)).asUInt
val s2_meta_errors = s2_meta.map(_.error).asUInt val s2_meta_corrected = s1_meta_decoded.map(m => RegEnable(m.corrected, s1_valid_not_nacked || s1_flush_valid || s1_probe).asTypeOf(new L1Metadata))
val s2_meta_error = s2_meta_errors.orR val s2_meta_error = s2_meta_errors.orR
val s2_flush_valid = s2_flush_valid_pre_tag_ecc && !s2_meta_error val s2_flush_valid = s2_flush_valid_pre_tag_ecc && !s2_meta_error
val s2_data = { val s2_data = {