From 62ccba304c102fb3606bf57495119ef41d89284b Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 8 Aug 2017 10:21:30 -0700 Subject: [PATCH] Perform tag error detectoin/correction in same cycle as RAM The tag RAMs tend to be fast, so take up some of the slack. This makes s2_nack faster. --- src/main/scala/rocket/DCache.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index e83796ea..17e50085 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -207,9 +207,9 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val s2_write = isWrite(s2_req.cmd) val s2_readwrite = s2_read || s2_write val s2_flush_valid_pre_tag_ecc = RegNext(s1_flush_valid) - val s2_meta = s1_meta.map(RegEnable(_, s1_valid_not_nacked || s1_flush_valid || s1_probe)).map(tECC.decode(_)) - val s2_meta_corrected = s2_meta.map(_.corrected.asTypeOf(new L1Metadata)) - val s2_meta_errors = s2_meta.map(_.error).asUInt + val s1_meta_decoded = s1_meta.map(tECC.decode(_)) + val s2_meta_errors = s1_meta_decoded.map(m => RegEnable(m.error, s1_valid_not_nacked || s1_flush_valid || s1_probe)).asUInt + val s2_meta_corrected = s1_meta_decoded.map(m => RegEnable(m.corrected, s1_valid_not_nacked || s1_flush_valid || s1_probe).asTypeOf(new L1Metadata)) val s2_meta_error = s2_meta_errors.orR val s2_flush_valid = s2_flush_valid_pre_tag_ecc && !s2_meta_error val s2_data = {