riscv/rocket-chip
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fixed cache controller flush unit deadlock

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This commit is contained in:
Henry Cook 2012-03-11 18:36:26 -07:00
parent ea0775643b
commit 6229a33dc4
1 changed files with 2 additions and 2 deletions
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4
rocket/src/main/scala/nbdcache.scala
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@ -722,8 +722,8 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
// reset and flush unit // reset and flush unit
val flusher = new FlushUnit(lines) val flusher = new FlushUnit(lines)
val flushed = Reg(resetVal = Bool(true)) val flushed = Reg(resetVal = Bool(true))
flushed := flushed && (!r_cpu_req_val_ || r_req_flush) || r_cpu_req_val_ && r_req_flush && mshr.io.fence_rdy && flusher.io.req.ready flushed := flushed && (!r_cpu_req_val || r_req_flush) || r_cpu_req_val && r_req_flush && mshr.io.fence_rdy && flusher.io.req.ready
flusher.io.req.valid := r_cpu_req_val_ && r_req_flush && mshr.io.fence_rdy && !flushed flusher.io.req.valid := r_cpu_req_val && r_req_flush && mshr.io.fence_rdy && !flushed
flusher.io.mshr_req.ready := mshr.io.req.ready flusher.io.mshr_req.ready := mshr.io.req.ready
when (io.cpu.req_val) { when (io.cpu.req_val) {