From 6229a33dc488731da5ba2bf5166146b319581a97 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Sun, 11 Mar 2012 18:36:26 -0700 Subject: [PATCH] fixed cache controller flush unit deadlock --- rocket/src/main/scala/nbdcache.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index fd76bbaf..4c9542d5 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -722,8 +722,8 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence { // reset and flush unit val flusher = new FlushUnit(lines) val flushed = Reg(resetVal = Bool(true)) - flushed := flushed && (!r_cpu_req_val_ || r_req_flush) || r_cpu_req_val_ && r_req_flush && mshr.io.fence_rdy && flusher.io.req.ready - flusher.io.req.valid := r_cpu_req_val_ && r_req_flush && mshr.io.fence_rdy && !flushed + flushed := flushed && (!r_cpu_req_val || r_req_flush) || r_cpu_req_val && r_req_flush && mshr.io.fence_rdy && flusher.io.req.ready + flusher.io.req.valid := r_cpu_req_val && r_req_flush && mshr.io.fence_rdy && !flushed flusher.io.mshr_req.ready := mshr.io.req.ready when (io.cpu.req_val) {