riscv/rocket-chip
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Invalidate TL error bit in D$ once progress is made

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This commit is contained in:
Andrew Waterman 2017-11-07 00:52:18 -08:00
parent d8d4504995
commit 6176b348dc
1 changed files with 1 additions and 0 deletions
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src/main/scala/rocket/DCache.scala
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@ -305,6 +305,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
} }
when (lrscCount > 0) { lrscCount := lrscCount - 1 } when (lrscCount > 0) { lrscCount := lrscCount - 1 }
when ((s2_valid_masked && lrscCount > 0) || io.cpu.invalidate_lr) { lrscCount := 0 } when ((s2_valid_masked && lrscCount > 0) || io.cpu.invalidate_lr) { lrscCount := 0 }
when (s2_valid_masked || io.cpu.invalidate_lr) { tl_error_valid := false }
// don't perform data correction if it might clobber a recent store // don't perform data correction if it might clobber a recent store
val s2_correct = s2_data_error && !any_pstore_valid && !RegNext(any_pstore_valid) && Bool(usingDataScratchpad) val s2_correct = s2_data_error && !any_pstore_valid && !RegNext(any_pstore_valid) && Bool(usingDataScratchpad)