Merge remote-tracking branch 'origin/master' into refactored_rbb

src/main/scala/coreplex/HasTiles.scala

@@ -3,6 +3,7 @@
 package freechips.rocketchip.coreplex
 
 import Chisel._
+import chisel3.experimental.dontTouch
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.interrupts._
@@ -37,9 +38,9 @@ trait HasTilesModuleImp extends LazyModuleImp
     vectors.head.getWidth
   }
 
-  val tile_inputs = Wire(Vec(outer.nTiles, new ClockedTileInputs()(p.alterPartial {
+  val tile_inputs = dontTouch(Wire(Vec(outer.nTiles, new ClockedTileInputs()(p.alterPartial {
     case SharedMemoryTLEdge => outer.sharedMemoryTLEdge
-  })))
+  })))) // dontTouch keeps constant prop from sucking these signals into the tile
 
   // Unconditionally wire up the non-diplomatic tile inputs
   outer.tiles.map(_.module).zip(tile_inputs).foreach { case(tile, wire) =>

src/main/scala/coreplex/RocketCoreplex.scala

@@ -118,18 +118,14 @@ trait HasRocketTiles extends HasTiles
     def tileSlaveBuffering: TLInwardNode = rocket {
       val slaveBuffer  = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none))
       crossing.crossingType match {
-        case _: SynchronousCrossing  => rocket.slaveNode // requirement already checked
+        case RationalCrossing(_) if (tp.boundaryBuffers) => rocket.slaveNode :*= slaveBuffer.node
-        case _: AsynchronousCrossing => rocket.slaveNode
+        case _ => rocket.slaveNode
-        case _: RationalCrossing =>
-          if (tp.boundaryBuffers) {
-            DisableMonitors { implicit p => rocket.slaveNode :*= slaveBuffer.node }
-          } else {
-            rocket.slaveNode
-          }
       }
     }
 
-    pbus.toTile(tp.name) { implicit p => crossing.slave.adapt(this)(tileSlaveBuffering :*= rocket.crossTLIn) }
+    pbus.toTile(tp.name) { implicit p => crossing.slave.adapt(this)( DisableMonitors { implicit p =>
+      tileSlaveBuffering :*= rocket.crossTLIn
+    })}
 
     // Handle all the different types of interrupts crossing to or from the tile:
     // 1. Debug interrupt is definitely asynchronous in all cases.
@@ -151,7 +147,7 @@ trait HasRocketTiles extends HasTiles
     if (tp.core.useVM) periphIntNode := plic.intnode // seip
 
     // 3. local interrupts  never cross 
-    // this.intInwardNode is wired up externally     // lip
+    // rocket.intInwardNode is wired up externally     // lip
 
     // 4. conditional crossing from core to PLIC
     FlipRendering { implicit p =>

src/main/scala/regmapper/RegField.scala

@@ -100,12 +100,12 @@ object RegField
 
   // This RegField wraps an explicit register
   // (e.g. Black-Boxed Register) to create a R/W register.
-  def rwReg(n: Int, bb: SimpleRegIO) : RegField =
+  def rwReg(n: Int, bb: SimpleRegIO, name: String = "", description: String = "") : RegField =
     RegField(n, bb.q, RegWriteFn((valid, data) => {
       bb.en := valid
       bb.d := data
       Bool(true)
-    }))
+    }), name, description)
 
   // Create byte-sized read-write RegFields out of a large UInt register.
   // It is updated when any of the bytes are written. Because the RegFields

src/main/scala/rocket/HellaCache.scala

@@ -4,6 +4,7 @@
 package freechips.rocketchip.rocket
 
 import Chisel._
+import chisel3.experimental.dontTouch
 import freechips.rocketchip.config.{Parameters, Field}
 import freechips.rocketchip.coreplex._
 import freechips.rocketchip.diplomacy._
@@ -184,6 +185,7 @@ class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
   implicit val edge = outer.node.edges.out(0)
   val (tl_out, _) = outer.node.out(0)
   val io = IO(new HellaCacheBundle(outer))
+  dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals
 
   private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allUncacheable)
   fifoManagers.foreach { m =>
@@ -257,11 +259,12 @@ class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters)
 
   val metabits = rstVal.getWidth
   val tag_array = SeqMem(nSets, Vec(nWays, UInt(width = metabits)))
-  when (rst || io.write.valid) {
+  val wen = rst || io.write.valid
+  when (wen) {
     tag_array.write(waddr, Vec.fill(nWays)(wdata), wmask)
   }
-  io.resp := tag_array.read(io.read.bits.idx, io.read.valid).map(rstVal.fromBits(_))
+  io.resp := tag_array.read(io.read.bits.idx, io.read.fire()).map(rstVal.fromBits(_))
 
-  io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
+  io.read.ready := !wen // so really this could be a 6T RAM
   io.write.ready := !rst
 }

src/main/scala/tile/BaseTile.scala

@@ -135,7 +135,6 @@ abstract class BaseTile(tileParams: TileParams, val crossing: CoreplexClockCross
   protected val tlMasterXbar = LazyModule(new TLXbar)
   protected val tlSlaveXbar = LazyModule(new TLXbar)
   protected val intXbar = LazyModule(new IntXbar)
-  protected val intSinkNode = IntSinkNode(IntSinkPortSimple())
 
   def connectTLSlave(node: TLNode, bytes: Int) {
     DisableMonitors { implicit p =>

src/main/scala/tile/Interrupts.scala

@@ -22,6 +22,7 @@ class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) {
 trait HasExternalInterrupts { this: BaseTile =>
 
   val intInwardNode = intXbar.intnode
+  protected val intSinkNode = IntSinkNode(IntSinkPortSimple())
   intSinkNode := intXbar.intnode
 
   val intcDevice = new Device {

src/main/scala/tile/RocketTile.scala

@@ -66,7 +66,7 @@ class RocketTile(
   // TODO: this doesn't block other masters, e.g. RoCCs
   tlOtherMastersNode := tile_master_blocker.map { _.node := tlMasterXbar.node } getOrElse { tlMasterXbar.node }
   masterNode :=* tlOtherMastersNode
-  tlSlaveXbar.node :*= slaveNode
+  DisableMonitors { implicit p => tlSlaveXbar.node :*= slaveNode }
 
   def findScratchpadFromICache: Option[AddressSet] = dtim_adapter.map { s =>
     val finalNode = frontend.masterNode.edges.out.head.manager.managers.find(_.nodePath.last == s.node)

src/main/scala/util/Misc.scala

@@ -4,7 +4,7 @@
 package freechips.rocketchip.util
 
 import Chisel._
-import chisel3.experimental.{dontTouch, RawModule}
+import chisel3.experimental.{ChiselAnnotation, RawModule}
 import freechips.rocketchip.config.Parameters
 import scala.math._
 
@@ -26,6 +26,13 @@ class ParameterizedBundle(implicit p: Parameters) extends Bundle {
 trait DontTouch {
   self: RawModule =>
 
+  def dontTouch(data: Data): Unit = data match {
+    case agg: Aggregate =>
+      agg.getElements.foreach(dontTouch)
+    case elt: Element =>
+      annotate(ChiselAnnotation(elt, classOf[firrtl.Transform], "DONTtouch!"))
+  }
+
   /** Marks every port as don't touch
     *
     * @note This method can only be called after the Module has been fully constructed
@@ -35,6 +42,11 @@ trait DontTouch {
     self.getModulePorts.foreach(dontTouch(_))
     self
   }
+
+  def dontTouchPortsExcept(f: Data => Boolean): this.type = {
+    self.getModulePorts.filterNot(f).foreach(dontTouch(_))
+    self
+  }
 }
 
 trait Clocked extends Bundle {