From 847efde385ed10cc3fdae8514fb5fc362abe5e82 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 5 Jan 2018 12:47:41 -0800 Subject: [PATCH 1/8] coreplex: dontTouch the tile_inputs wire --- src/main/scala/coreplex/HasTiles.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/coreplex/HasTiles.scala b/src/main/scala/coreplex/HasTiles.scala index 82436651..49a958f8 100644 --- a/src/main/scala/coreplex/HasTiles.scala +++ b/src/main/scala/coreplex/HasTiles.scala @@ -3,6 +3,7 @@ package freechips.rocketchip.coreplex import Chisel._ +import chisel3.experimental.dontTouch import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.interrupts._ @@ -37,9 +38,9 @@ trait HasTilesModuleImp extends LazyModuleImp vectors.head.getWidth } - val tile_inputs = Wire(Vec(outer.nTiles, new ClockedTileInputs()(p.alterPartial { + val tile_inputs = dontTouch(Wire(Vec(outer.nTiles, new ClockedTileInputs()(p.alterPartial { case SharedMemoryTLEdge => outer.sharedMemoryTLEdge - }))) + })))) // dontTouch keeps constant prop from sucking these signals into the tile // Unconditionally wire up the non-diplomatic tile inputs outer.tiles.map(_.module).zip(tile_inputs).foreach { case(tile, wire) => From 4853d1355f6b30574f5d3c9f0339d5bfa1b610d1 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 5 Jan 2018 12:50:24 -0800 Subject: [PATCH 2/8] rocket: dontTouch HellaCache.io.cpu.resp --- src/main/scala/rocket/HellaCache.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index 2467a670..bffbcd82 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -4,6 +4,7 @@ package freechips.rocketchip.rocket import Chisel._ +import chisel3.experimental.dontTouch import freechips.rocketchip.config.{Parameters, Field} import freechips.rocketchip.coreplex._ import freechips.rocketchip.diplomacy._ @@ -184,6 +185,7 @@ class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) implicit val edge = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle(outer)) + dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allUncacheable) fifoManagers.foreach { m => From b77b93b0b4d927bc2b007a83428165c040f54c35 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 2 Oct 2017 19:34:51 -0700 Subject: [PATCH 3/8] util: dontTouchPortsExcept --- src/main/scala/util/Misc.scala | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/main/scala/util/Misc.scala b/src/main/scala/util/Misc.scala index 8ff24fb9..14a2510d 100644 --- a/src/main/scala/util/Misc.scala +++ b/src/main/scala/util/Misc.scala @@ -35,6 +35,11 @@ trait DontTouch { self.getModulePorts.foreach(dontTouch(_)) self } + + def dontTouchPortsExcept(f: Data => Boolean): this.type = { + self.getModulePorts.filterNot(f).foreach(dontTouch(_)) + self + } } trait Clocked extends Bundle { From 8425086f98ab1ebd90c74ca8907cc36f486fea6e Mon Sep 17 00:00:00 2001 From: Albert Huntington Date: Fri, 5 Jan 2018 16:59:58 -0800 Subject: [PATCH 4/8] Allow rwReg to pass name and description to RegField for documentation. --- src/main/scala/regmapper/RegField.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/regmapper/RegField.scala b/src/main/scala/regmapper/RegField.scala index 16212c24..4f618ca4 100644 --- a/src/main/scala/regmapper/RegField.scala +++ b/src/main/scala/regmapper/RegField.scala @@ -100,12 +100,12 @@ object RegField // This RegField wraps an explicit register // (e.g. Black-Boxed Register) to create a R/W register. - def rwReg(n: Int, bb: SimpleRegIO) : RegField = + def rwReg(n: Int, bb: SimpleRegIO, name: String = "", description: String = "") : RegField = RegField(n, bb.q, RegWriteFn((valid, data) => { bb.en := valid bb.d := data Bool(true) - })) + }), name, description) // Create byte-sized read-write RegFields out of a large UInt register. // It is updated when any of the bytes are written. Because the RegFields From 5075a93e6c831447e1097633ff6507f00c856014 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 8 Jan 2018 15:58:28 -0800 Subject: [PATCH 5/8] util: dontTouch work-around for zero width aggregates --- src/main/scala/util/Misc.scala | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/main/scala/util/Misc.scala b/src/main/scala/util/Misc.scala index 14a2510d..0025f187 100644 --- a/src/main/scala/util/Misc.scala +++ b/src/main/scala/util/Misc.scala @@ -4,7 +4,7 @@ package freechips.rocketchip.util import Chisel._ -import chisel3.experimental.{dontTouch, RawModule} +import chisel3.experimental.{ChiselAnnotation, RawModule} import freechips.rocketchip.config.Parameters import scala.math._ @@ -26,6 +26,13 @@ class ParameterizedBundle(implicit p: Parameters) extends Bundle { trait DontTouch { self: RawModule => + def dontTouch(data: Data): Unit = data match { + case agg: Aggregate => + agg.getElements.foreach(dontTouch) + case elt: Element => + annotate(ChiselAnnotation(elt, classOf[firrtl.Transform], "DONTtouch!")) + } + /** Marks every port as don't touch * * @note This method can only be called after the Module has been fully constructed From 11e5b620f87c40984072ad5d745c6a336b7fee98 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 8 Jan 2018 18:41:55 -0800 Subject: [PATCH 6/8] tile: disable more monitors on slave port --- src/main/scala/coreplex/RocketCoreplex.scala | 16 ++++++---------- src/main/scala/tile/RocketTile.scala | 2 +- 2 files changed, 7 insertions(+), 11 deletions(-) diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala index a070123b..db3702bd 100644 --- a/src/main/scala/coreplex/RocketCoreplex.scala +++ b/src/main/scala/coreplex/RocketCoreplex.scala @@ -118,18 +118,14 @@ trait HasRocketTiles extends HasTiles def tileSlaveBuffering: TLInwardNode = rocket { val slaveBuffer = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none)) crossing.crossingType match { - case _: SynchronousCrossing => rocket.slaveNode // requirement already checked - case _: AsynchronousCrossing => rocket.slaveNode - case _: RationalCrossing => - if (tp.boundaryBuffers) { - DisableMonitors { implicit p => rocket.slaveNode :*= slaveBuffer.node } - } else { - rocket.slaveNode - } + case RationalCrossing(_) if (tp.boundaryBuffers) => rocket.slaveNode :*= slaveBuffer.node + case _ => rocket.slaveNode } } - pbus.toTile(tp.name) { implicit p => crossing.slave.adapt(this)(tileSlaveBuffering :*= rocket.crossTLIn) } + pbus.toTile(tp.name) { implicit p => crossing.slave.adapt(this)( DisableMonitors { implicit p => + tileSlaveBuffering :*= rocket.crossTLIn + })} // Handle all the different types of interrupts crossing to or from the tile: // 1. Debug interrupt is definitely asynchronous in all cases. @@ -151,7 +147,7 @@ trait HasRocketTiles extends HasTiles if (tp.core.useVM) periphIntNode := plic.intnode // seip // 3. local interrupts never cross - // this.intInwardNode is wired up externally // lip + // rocket.intInwardNode is wired up externally // lip // 4. conditional crossing from core to PLIC FlipRendering { implicit p => diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index e2126ebe..81e16b63 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -66,7 +66,7 @@ class RocketTile( // TODO: this doesn't block other masters, e.g. RoCCs tlOtherMastersNode := tile_master_blocker.map { _.node := tlMasterXbar.node } getOrElse { tlMasterXbar.node } masterNode :=* tlOtherMastersNode - tlSlaveXbar.node :*= slaveNode + DisableMonitors { implicit p => tlSlaveXbar.node :*= slaveNode } def findScratchpadFromICache: Option[AddressSet] = dtim_adapter.map { s => val finalNode = frontend.masterNode.edges.out.head.manager.managers.find(_.nodePath.last == s.node) From 15c54b1c5a1c106983ee44a12510b8200dabc3ac Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 8 Jan 2018 19:38:10 -0800 Subject: [PATCH 7/8] tile: intSinkNode belongs in HasExternalInterrupts --- src/main/scala/tile/BaseTile.scala | 1 - src/main/scala/tile/Interrupts.scala | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index c8c669a2..40f2b8da 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -135,7 +135,6 @@ abstract class BaseTile(tileParams: TileParams, val crossing: CoreplexClockCross protected val tlMasterXbar = LazyModule(new TLXbar) protected val tlSlaveXbar = LazyModule(new TLXbar) protected val intXbar = LazyModule(new IntXbar) - protected val intSinkNode = IntSinkNode(IntSinkPortSimple()) def connectTLSlave(node: TLNode, bytes: Int) { DisableMonitors { implicit p => diff --git a/src/main/scala/tile/Interrupts.scala b/src/main/scala/tile/Interrupts.scala index 13c5d64e..6e81f109 100644 --- a/src/main/scala/tile/Interrupts.scala +++ b/src/main/scala/tile/Interrupts.scala @@ -22,6 +22,7 @@ class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) { trait HasExternalInterrupts { this: BaseTile => val intInwardNode = intXbar.intnode + protected val intSinkNode = IntSinkNode(IntSinkPortSimple()) intSinkNode := intXbar.intnode val intcDevice = new Device { From c152962642b84b808a5f097eb9351745a17a9334 Mon Sep 17 00:00:00 2001 From: pentin-as <30556064+pentin-as@users.noreply.github.com> Date: Tue, 9 Jan 2018 16:06:43 -0500 Subject: [PATCH 8/8] Dual-port RAM replaced with single-port RAM for tag_array in HellaCache (#1181) In accordance with https://github.com/freechipsproject/chisel3/issues/752 --- src/main/scala/rocket/HellaCache.scala | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index 2467a670..c2b21e3a 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -257,11 +257,12 @@ class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) val metabits = rstVal.getWidth val tag_array = SeqMem(nSets, Vec(nWays, UInt(width = metabits))) - when (rst || io.write.valid) { + val wen = rst || io.write.valid + when (wen) { tag_array.write(waddr, Vec.fill(nWays)(wdata), wmask) } - io.resp := tag_array.read(io.read.bits.idx, io.read.valid).map(rstVal.fromBits(_)) + io.resp := tag_array.read(io.read.bits.idx, io.read.fire()).map(rstVal.fromBits(_)) - io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM + io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst }