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tilelink2: add an intermediate type for simple factories

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This commit is contained in:
Wesley W. Terpstra 2016-08-29 17:53:31 -07:00
parent 967d8f108c
commit 5f7711a0c0
4 changed files with 9 additions and 3 deletions
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6
uncore/src/main/scala/tilelink2/Bases.scala
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@ -39,6 +39,12 @@ abstract class TLFactory
} }
} }
// Use this if you have only one node => makes factory adapters possible
abstract class TLSimpleFactory extends TLFactory
{
def node: TLBaseNode
}
abstract class TLModule(factory: TLFactory) extends Module abstract class TLModule(factory: TLFactory) extends Module
{ {
override def desiredName = factory.getClass.getName.split('.').last override def desiredName = factory.getClass.getName.split('.').last

2
uncore/src/main/scala/tilelink2/RegisterRouter.scala
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@ -59,7 +59,7 @@ object TLRegisterNode
// register mapped device from a totally abstract register mapped device. // register mapped device from a totally abstract register mapped device.
// See GPIO.scala in this directory for an example // See GPIO.scala in this directory for an example
abstract class TLRegFactory(address: AddressSet, concurrency: Option[Int], beatBytes: Int) extends TLFactory abstract class TLRegFactory(address: AddressSet, concurrency: Option[Int], beatBytes: Int) extends TLSimpleFactory
{ {
val node = TLRegisterNode(address, concurrency, beatBytes) val node = TLRegisterNode(address, concurrency, beatBytes)
} }

2
uncore/src/main/scala/tilelink2/SRAM.scala
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@ -4,7 +4,7 @@ package uncore.tilelink2
import Chisel._ import Chisel._
class TLRAM(address: AddressSet, beatBytes: Int = 4) extends TLFactory class TLRAM(address: AddressSet, beatBytes: Int = 4) extends TLSimpleFactory
{ {
val node = TLManagerNode(beatBytes, TLManagerParameters( val node = TLManagerNode(beatBytes, TLManagerParameters(
address = List(address), address = List(address),

2
uncore/src/main/scala/tilelink2/Xbar.scala
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@ -13,7 +13,7 @@ object TLXbar
} }
} }
class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extends TLFactory class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extends TLSimpleFactory
{ {
def mapInputIds (ports: Seq[TLClientPortParameters ]) = assignRanges(ports.map(_.endSourceId)) def mapInputIds (ports: Seq[TLClientPortParameters ]) = assignRanges(ports.map(_.endSourceId))
def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId)) def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId))