From 5f7711a0c0edcaace765f30bb5ed4394a6ea2ff8 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Mon, 29 Aug 2016 17:53:31 -0700 Subject: [PATCH] tilelink2: add an intermediate type for simple factories --- uncore/src/main/scala/tilelink2/Bases.scala | 6 ++++++ uncore/src/main/scala/tilelink2/RegisterRouter.scala | 2 +- uncore/src/main/scala/tilelink2/SRAM.scala | 2 +- uncore/src/main/scala/tilelink2/Xbar.scala | 2 +- 4 files changed, 9 insertions(+), 3 deletions(-) diff --git a/uncore/src/main/scala/tilelink2/Bases.scala b/uncore/src/main/scala/tilelink2/Bases.scala index c9333886..dcd0caf3 100644 --- a/uncore/src/main/scala/tilelink2/Bases.scala +++ b/uncore/src/main/scala/tilelink2/Bases.scala @@ -39,6 +39,12 @@ abstract class TLFactory } } +// Use this if you have only one node => makes factory adapters possible +abstract class TLSimpleFactory extends TLFactory +{ + def node: TLBaseNode +} + abstract class TLModule(factory: TLFactory) extends Module { override def desiredName = factory.getClass.getName.split('.').last diff --git a/uncore/src/main/scala/tilelink2/RegisterRouter.scala b/uncore/src/main/scala/tilelink2/RegisterRouter.scala index cf9ae70f..35ff80d5 100644 --- a/uncore/src/main/scala/tilelink2/RegisterRouter.scala +++ b/uncore/src/main/scala/tilelink2/RegisterRouter.scala @@ -59,7 +59,7 @@ object TLRegisterNode // register mapped device from a totally abstract register mapped device. // See GPIO.scala in this directory for an example -abstract class TLRegFactory(address: AddressSet, concurrency: Option[Int], beatBytes: Int) extends TLFactory +abstract class TLRegFactory(address: AddressSet, concurrency: Option[Int], beatBytes: Int) extends TLSimpleFactory { val node = TLRegisterNode(address, concurrency, beatBytes) } diff --git a/uncore/src/main/scala/tilelink2/SRAM.scala b/uncore/src/main/scala/tilelink2/SRAM.scala index 0b3ff2f5..77b10dbc 100644 --- a/uncore/src/main/scala/tilelink2/SRAM.scala +++ b/uncore/src/main/scala/tilelink2/SRAM.scala @@ -4,7 +4,7 @@ package uncore.tilelink2 import Chisel._ -class TLRAM(address: AddressSet, beatBytes: Int = 4) extends TLFactory +class TLRAM(address: AddressSet, beatBytes: Int = 4) extends TLSimpleFactory { val node = TLManagerNode(beatBytes, TLManagerParameters( address = List(address), diff --git a/uncore/src/main/scala/tilelink2/Xbar.scala b/uncore/src/main/scala/tilelink2/Xbar.scala index 20325196..f4ba477d 100644 --- a/uncore/src/main/scala/tilelink2/Xbar.scala +++ b/uncore/src/main/scala/tilelink2/Xbar.scala @@ -13,7 +13,7 @@ object TLXbar } } -class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extends TLFactory +class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extends TLSimpleFactory { def mapInputIds (ports: Seq[TLClientPortParameters ]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId))