tilelink2: add an intermediate type for simple factories

uncore/src/main/scala/tilelink2/Bases.scala

@@ -39,6 +39,12 @@ abstract class TLFactory
   }
 }
 
+// Use this if you have only one node => makes factory adapters possible
+abstract class TLSimpleFactory extends TLFactory
+{
+  def node: TLBaseNode
+}
+
 abstract class TLModule(factory: TLFactory) extends Module
 {
   override def desiredName = factory.getClass.getName.split('.').last

uncore/src/main/scala/tilelink2/RegisterRouter.scala

@@ -59,7 +59,7 @@ object TLRegisterNode
 // register mapped device from a totally abstract register mapped device.
 // See GPIO.scala in this directory for an example
 
-abstract class TLRegFactory(address: AddressSet, concurrency: Option[Int], beatBytes: Int) extends TLFactory
+abstract class TLRegFactory(address: AddressSet, concurrency: Option[Int], beatBytes: Int) extends TLSimpleFactory
 {
   val node = TLRegisterNode(address, concurrency, beatBytes)
 }

uncore/src/main/scala/tilelink2/SRAM.scala

@@ -4,7 +4,7 @@ package uncore.tilelink2
 
 import Chisel._
 
-class TLRAM(address: AddressSet, beatBytes: Int = 4) extends TLFactory
+class TLRAM(address: AddressSet, beatBytes: Int = 4) extends TLSimpleFactory
 {
   val node = TLManagerNode(beatBytes, TLManagerParameters(
     address            = List(address),

uncore/src/main/scala/tilelink2/Xbar.scala

@@ -13,7 +13,7 @@ object TLXbar
   }
 }
 
-class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extends TLFactory
+class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extends TLSimpleFactory
 {
   def mapInputIds (ports: Seq[TLClientPortParameters ]) = assignRanges(ports.map(_.endSourceId))
   def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId))