riscv/rocket-chip
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Merge remote-tracking branch 'origin/master' into black_box_regs

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This commit is contained in:
Megan Wachs
2016-09-09 13:12:52 -07:00
parent fda4c2bd76 c4593d2034
commit 5f5989848c
11 changed files with 222 additions and 78 deletions
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14
src/main/scala/uncore/tilelink2/Example.scala
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@ -16,14 +16,22 @@ trait ExampleModule extends HasRegMap
{
val params: ExampleParams
val io: ExampleBundle
val interrupts: Vec[Bool]
val state = RegInit(UInt(0))
io.gpio := state
val pending = RegInit(UInt(0xf, width = 4))
regmap(0 -> Seq(RegField(params.num, state)))
io.gpio := state
interrupts := pending.toBools
regmap(
0 -> Seq(
RegField(params.num, state)),
1 -> Seq(
RegField.w1ToClear(4, pending, state)))
}
// Create a concrete TL2 version of the abstract Example slave
class TLExample(p: ExampleParams) extends TLRegisterRouter(p.address)(
class TLExample(p: ExampleParams) extends TLRegisterRouter(p.address, 4)(
new TLRegBundle(p, _) with ExampleBundle)(
new TLRegModule(p, _, _) with ExampleModule)