rocc: fix RoccExampleConfig

src/main/scala/coreplex/Configs.scala

@@ -163,18 +163,20 @@ class WithNBreakpoints(hwbp: Int) extends Config ((site, here, up) => {
 })
 
 class WithRoccExample extends Config((site, here, up) => {
-  case BuildRoCC => Seq(
-    RoCCParams(
-      opcodes = OpcodeSet.custom0,
-      generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
-    RoCCParams(
-      opcodes = OpcodeSet.custom1,
-      generator = (p: Parameters) => Module(new TranslatorExample()(p)),
-      nPTWPorts = 1),
-    RoCCParams(
-      opcodes = OpcodeSet.custom2,
-      generator = (p: Parameters) => Module(new CharacterCountExample()(p))))
-
+  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
+    r.copy(rocc = Seq(
+      RoCCParams(
+        opcodes = OpcodeSet.custom0,
+        generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
+      RoCCParams(
+         opcodes = OpcodeSet.custom1,
+         generator = (p: Parameters) => Module(new TranslatorExample()(p)),
+         nPTWPorts = 1),
+      RoCCParams(
+         opcodes = OpcodeSet.custom2,
+         generator = (p: Parameters) => Module(new CharacterCountExample()(p)))
+    ))
+  }
   case RoccMaxTaggedMemXacts => 1
 })
 

src/main/scala/tile/LegacyRoCC.scala

@@ -48,7 +48,7 @@ trait CanHaveLegacyRoccs extends CanHaveSharedFPU with CanHavePTW with HasTileLi
     }})))
 
   legacyRocc foreach { lr =>
-    tileBus.node := lr.masterNode
+    tileBus.node :=* lr.masterNode
     nPTWPorts += lr.nPTWPorts
     nDCachePorts += lr.nRocc
   }
@@ -66,7 +66,7 @@ trait CanHaveLegacyRoccsModule extends CanHaveSharedFPUModule
       None
     } foreach { lr =>
       fpu.io.cp_req <> lr.module.io.fpu.cp_req
-      fpu.io.cp_resp <> lr.module.io.fpu.cp_resp
+      lr.module.io.fpu.cp_resp <> fpu.io.cp_resp
     }
   }