229 lines
7.6 KiB
Scala
229 lines
7.6 KiB
Scala
// See LICENSE.SiFive for license details.
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// See LICENSE.Berkeley for license details.
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package coreplex
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import Chisel._
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import config._
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import diplomacy._
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import rocket._
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import tile._
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import uncore.converters._
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import uncore.devices._
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import uncore.tilelink2._
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import uncore.util._
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import util._
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class BaseCoreplexConfig extends Config ((site, here, up) => {
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case PAddrBits => 32
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case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
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case ASIdBits => 0
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case XLen => 64 // Applies to all cores
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case ResetVectorBits => site(PAddrBits)
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case MaxHartIdBits => log2Up(site(NTiles))
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case MaxPriorityLevels => 7
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case BuildCore => (p: Parameters) => new Rocket()(p)
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case RocketCrossing => SynchronousCrossing()
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case RocketTilesKey => Nil
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case DMKey => DefaultDebugModuleConfig(site(XLen))
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case NTiles => site(RocketTilesKey).size
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case CBusConfig => TLBusConfig(beatBytes = site(XLen)/8)
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case L1toL2Config => TLBusConfig(beatBytes = site(XLen)/8) // increase for more PCIe bandwidth
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case BootROMFile => "./bootrom/bootrom.img"
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case BroadcastConfig => BroadcastConfig()
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case BankedL2Config => BankedL2Config()
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case CacheBlockBytes => 64
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})
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class WithNBigCores(n: Int) extends Config((site, here, up) => {
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case RocketTilesKey => {
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val big = RocketTileParams(
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core = RocketCoreParams(mulDiv = Some(MulDivParams(
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mulUnroll = 8,
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mulEarlyOut = true,
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divEarlyOut = true))),
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dcache = Some(DCacheParams(
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rowBits = site(L1toL2Config).beatBytes*8,
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nMSHRs = 0,
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blockBytes = site(CacheBlockBytes))),
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icache = Some(ICacheParams(
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rowBits = site(L1toL2Config).beatBytes*8,
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blockBytes = site(CacheBlockBytes))))
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List.fill(n)(big) ++ up(RocketTilesKey, site)
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}
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})
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class WithNSmallCores(n: Int) extends Config((site, here, up) => {
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case RocketTilesKey => {
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val small = RocketTileParams(
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core = RocketCoreParams(useVM = false, fpu = None),
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btb = None,
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dcache = Some(DCacheParams(
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rowBits = site(L1toL2Config).beatBytes*8,
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nSets = 64,
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nWays = 1,
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nTLBEntries = 4,
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nMSHRs = 0,
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blockBytes = site(CacheBlockBytes))),
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icache = Some(ICacheParams(
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rowBits = site(L1toL2Config).beatBytes*8,
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nSets = 64,
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nWays = 1,
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nTLBEntries = 4,
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blockBytes = site(CacheBlockBytes))))
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List.fill(n)(small) ++ up(RocketTilesKey, site)
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}
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})
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class WithNBanksPerMemChannel(n: Int) extends Config((site, here, up) => {
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case BankedL2Config => up(BankedL2Config, site).copy(nBanksPerChannel = n)
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})
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class WithNTrackersPerBank(n: Int) extends Config((site, here, up) => {
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case BroadcastConfig => up(BroadcastConfig, site).copy(nTrackers = n)
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})
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// This is the number of icache sets for all Rocket tiles
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class WithL1ICacheSets(sets: Int) extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(icache = r.icache.map(_.copy(nSets = sets))) }
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})
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// This is the number of icache sets for all Rocket tiles
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class WithL1DCacheSets(sets: Int) extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(dcache = r.dcache.map(_.copy(nSets = sets))) }
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})
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class WithL1ICacheWays(ways: Int) extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(icache = r.icache.map(_.copy(nWays = ways)))
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}
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})
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class WithL1DCacheWays(ways: Int) extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(dcache = r.dcache.map(_.copy(nWays = ways)))
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}
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})
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class WithCacheBlockBytes(linesize: Int) extends Config((site, here, up) => {
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case CacheBlockBytes => linesize
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})
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class WithL2Cache extends Config(Parameters.empty) // TODO: re-add L2
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class WithL2Capacity(size_kb: Int) extends Config(Parameters.empty) // TODO: re-add L2
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class WithNL2Ways(n: Int) extends Config(Parameters.empty) // TODO: re-add L2
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class WithBufferlessBroadcastHub extends Config((site, here, up) => {
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case BroadcastConfig => up(BroadcastConfig, site).copy(bufferless = true)
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})
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/**
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* WARNING!!! IGNORE AT YOUR OWN PERIL!!!
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*
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* There is a very restrictive set of conditions under which the stateless
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* bridge will function properly. There can only be a single tile. This tile
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* MUST use the blocking data cache (L1D_MSHRS == 0) and MUST NOT have an
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* uncached channel capable of writes (i.e. a RoCC accelerator).
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*
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* This is because the stateless bridge CANNOT generate probes, so if your
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* system depends on coherence between channels in any way,
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* DO NOT use this configuration.
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*/
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class WithStatelessBridge extends Config((site, here, up) => {
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case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (q, _) =>
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implicit val p = q
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val cork = LazyModule(new TLCacheCork(unsafe = true))
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val ww = LazyModule(new TLWidthWidget(p(L1toL2Config).beatBytes))
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ww.node :*= cork.node
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(cork.node, ww.node)
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})
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})
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class WithRV32 extends Config((site, here, up) => {
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case XLen => 32
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(core = r.core.copy(
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mulDiv = Some(MulDivParams(mulUnroll = 8)),
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fpu = r.core.fpu.map(_.copy(divSqrt = false))))
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}
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})
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class WithNonblockingL1(nMSHRs: Int) extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(dcache = r.dcache.map(_.copy(nMSHRs = nMSHRs)))
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}
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})
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class WithNBreakpoints(hwbp: Int) extends Config ((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(core = r.core.copy(nBreakpoints = hwbp))
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}
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})
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class WithRoccExample extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(rocc = Seq(
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RoCCParams(
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opcodes = OpcodeSet.custom0,
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generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
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RoCCParams(
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opcodes = OpcodeSet.custom1,
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generator = (p: Parameters) => Module(new TranslatorExample()(p)),
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nPTWPorts = 1),
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RoCCParams(
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opcodes = OpcodeSet.custom2,
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generator = (p: Parameters) => Module(new CharacterCountExample()(p)))
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))
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}
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case RoccMaxTaggedMemXacts => 1
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})
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class WithDefaultBtb extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(btb = Some(BTBParams()))
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}
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})
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class WithFastMulDiv extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(core = r.core.copy(mulDiv = Some(
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MulDivParams(mulUnroll = 8, mulEarlyOut = (site(XLen) > 32), divEarlyOut = true)
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)))}
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})
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class WithoutMulDiv extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(core = r.core.copy(mulDiv = None))
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}
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})
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class WithoutFPU extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(core = r.core.copy(fpu = None))
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}
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})
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class WithFPUWithoutDivSqrt extends Config((site, here, up) => {
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case RocketTilesKey => up(RocketTilesKey, site) map { r =>
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r.copy(core = r.core.copy(fpu = r.core.fpu.map(_.copy(divSqrt = false))))
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}
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})
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class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {
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case BootROMFile => bootROMFile
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})
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class WithSynchronousRocketTiles extends Config((site, here, up) => {
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case RocketCrossing => SynchronousCrossing()
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})
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class WithAynchronousRocketTiles(depth: Int, sync: Int) extends Config((site, here, up) => {
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case RocketCrossing => AsynchronousCrossing(depth, sync)
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})
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class WithRationalRocketTiles extends Config((site, here, up) => {
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case RocketCrossing => RationalCrossing()
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})
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