riscv/rocket-chip
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rocc: fix RoccExampleConfig

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This commit is contained in:
Henry Cook
2017-05-16 16:44:53 -07:00
parent a19fc2549e
commit 5f22e91a7f
2 changed files with 16 additions and 14 deletions
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8
src/main/scala/coreplex/Configs.scala
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@@ -163,7 +163,8 @@ class WithNBreakpoints(hwbp: Int) extends Config ((site, here, up) => {
}) })
class WithRoccExample extends Config((site, here, up) => { class WithRoccExample extends Config((site, here, up) => {
case BuildRoCC => Seq( case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(rocc = Seq(
RoCCParams( RoCCParams(
opcodes = OpcodeSet.custom0, opcodes = OpcodeSet.custom0,
generator = (p: Parameters) => Module(new AccumulatorExample()(p))), generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
@@ -173,8 +174,9 @@ class WithRoccExample extends Config((site, here, up) => {
nPTWPorts = 1), nPTWPorts = 1),
RoCCParams( RoCCParams(
opcodes = OpcodeSet.custom2, opcodes = OpcodeSet.custom2,
generator = (p: Parameters) => Module(new CharacterCountExample()(p)))) generator = (p: Parameters) => Module(new CharacterCountExample()(p)))
))
}
case RoccMaxTaggedMemXacts => 1 case RoccMaxTaggedMemXacts => 1
}) })

4
src/main/scala/tile/LegacyRoCC.scala
View File

@@ -48,7 +48,7 @@ trait CanHaveLegacyRoccs extends CanHaveSharedFPU with CanHavePTW with HasTileLi
}}))) }})))
legacyRocc foreach { lr => legacyRocc foreach { lr =>
tileBus.node := lr.masterNode tileBus.node :=* lr.masterNode
nPTWPorts += lr.nPTWPorts nPTWPorts += lr.nPTWPorts
nDCachePorts += lr.nRocc nDCachePorts += lr.nRocc
} }
@@ -66,7 +66,7 @@ trait CanHaveLegacyRoccsModule extends CanHaveSharedFPUModule
None None
} foreach { lr => } foreach { lr =>
fpu.io.cp_req <> lr.module.io.fpu.cp_req fpu.io.cp_req <> lr.module.io.fpu.cp_req
fpu.io.cp_resp <> lr.module.io.fpu.cp_resp lr.module.io.fpu.cp_resp <> fpu.io.cp_resp
} }
} }