riscv/rocket-chip
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Merge pull request #10 from wsong83/fix

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L1 D$ writeback unit, reduce re-read data array
This commit is contained in:
Henry Cook
2015-07-06 15:18:49 -07:00
parent 5362e2bbbd 4db60d9e9d
commit 5ed2899e56
1 changed files with 8 additions and 6 deletions
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6
rocket/src/main/scala/nbdcache.scala
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@@ -409,11 +409,13 @@ class WritebackUnit extends L1HellaCacheModule {
} }
when (r2_data_req_fired) { when (r2_data_req_fired) {
io.release.valid := beat_done io.release.valid := beat_done
when(beat_done) {
when(!io.release.ready) { when(!io.release.ready) {
r1_data_req_fired := false r1_data_req_fired := false
r2_data_req_fired := false r2_data_req_fired := false
data_req_cnt := data_req_cnt - Mux[UInt](Bool(refillCycles > 1) && r1_data_req_fired, 2, 1) data_req_cnt := data_req_cnt - Mux[UInt](Bool(refillCycles > 1) && r1_data_req_fired, 2, 1)
} .elsewhen(beat_done) { if(refillCyclesPerBeat > 1) buf_v := 0 } } .otherwise { if(refillCyclesPerBeat > 1) buf_v := 0 }
}
when(!r1_data_req_fired) { when(!r1_data_req_fired) {
// We're done if this is the final data request and the Release can be sent // We're done if this is the final data request and the Release can be sent
active := data_req_cnt < UInt(refillCycles) || !io.release.ready active := data_req_cnt < UInt(refillCycles) || !io.release.ready
@@ -880,7 +882,7 @@ class HellaCache extends L1HellaCacheModule {
val s2_recycle_ecc = (s2_valid || s2_replay) && s2_hit && s2_data_correctable val s2_recycle_ecc = (s2_valid || s2_replay) && s2_hit && s2_data_correctable
val s2_recycle_next = Reg(init=Bool(false)) val s2_recycle_next = Reg(init=Bool(false))
when (s1_valid || s1_replay) { s2_recycle_next := (s1_valid || s1_replay) && s2_recycle_ecc } when (s1_valid || s1_replay) { s2_recycle_next := s2_recycle_ecc }
s2_recycle := s2_recycle_ecc || s2_recycle_next s2_recycle := s2_recycle_ecc || s2_recycle_next
// after a nack, block until nack condition resolves to save energy // after a nack, block until nack condition resolves to save energy