From b6e68773fd1ad828043945471feda64424380032 Mon Sep 17 00:00:00 2001 From: Wei Song Date: Sat, 30 May 2015 16:25:27 +0100 Subject: [PATCH 1/2] nbdcache, writeback unit: when release is not ready and data is not ready for a beat too, no need to re-read data array. --- rocket/src/main/scala/nbdcache.scala | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 95cde564..29af64c0 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -409,11 +409,13 @@ class WritebackUnit extends L1HellaCacheModule { } when (r2_data_req_fired) { io.release.valid := beat_done - when(!io.release.ready) { - r1_data_req_fired := false - r2_data_req_fired := false - data_req_cnt := data_req_cnt - Mux[UInt](Bool(refillCycles > 1) && r1_data_req_fired, 2, 1) - } .elsewhen(beat_done) { if(refillCyclesPerBeat > 1) buf_v := 0 } + when(beat_done) { + when(!io.release.ready) { + r1_data_req_fired := false + r2_data_req_fired := false + data_req_cnt := data_req_cnt - Mux[UInt](Bool(refillCycles > 1) && r1_data_req_fired, 2, 1) + } .otherwise { if(refillCyclesPerBeat > 1) buf_v := 0 } + } when(!r1_data_req_fired) { // We're done if this is the final data request and the Release can be sent active := data_req_cnt < UInt(refillCycles) || !io.release.ready From 4db60d9e9d28be5d9116272b64a5d2e32a6106cc Mon Sep 17 00:00:00 2001 From: Wei Song Date: Tue, 2 Jun 2015 22:06:12 +0100 Subject: [PATCH 2/2] code clean in dcache, no need to check the condition twice. --- rocket/src/main/scala/nbdcache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 29af64c0..806a0074 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -882,7 +882,7 @@ class HellaCache extends L1HellaCacheModule { val s2_recycle_ecc = (s2_valid || s2_replay) && s2_hit && s2_data_correctable val s2_recycle_next = Reg(init=Bool(false)) - when (s1_valid || s1_replay) { s2_recycle_next := (s1_valid || s1_replay) && s2_recycle_ecc } + when (s1_valid || s1_replay) { s2_recycle_next := s2_recycle_ecc } s2_recycle := s2_recycle_ecc || s2_recycle_next // after a nack, block until nack condition resolves to save energy