riscv/rocket-chip
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Fix an apparently benign PC sign-extension bug

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This commit is contained in:
Andrew Waterman 2015-06-11 16:08:18 -07:00
parent 6a9390c50e
commit 5e009ecc75
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/dpath.scala
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@ -226,7 +226,7 @@ class Datapath extends CoreModule
io.fpu.dmem_resp_tag := dmem_resp_waddr io.fpu.dmem_resp_tag := dmem_resp_waddr
io.ctrl.mem_br_taken := mem_reg_wdata(0) io.ctrl.mem_br_taken := mem_reg_wdata(0)
val mem_br_target = mem_reg_pc + val mem_br_target = mem_reg_pc.toSInt +
Mux(io.ctrl.mem_ctrl.branch && io.ctrl.mem_br_taken, imm(IMM_SB, mem_reg_inst), Mux(io.ctrl.mem_ctrl.branch && io.ctrl.mem_br_taken, imm(IMM_SB, mem_reg_inst),
Mux(io.ctrl.mem_ctrl.jal, imm(IMM_UJ, mem_reg_inst), SInt(4))) Mux(io.ctrl.mem_ctrl.jal, imm(IMM_UJ, mem_reg_inst), SInt(4)))
val mem_npc = (Mux(io.ctrl.mem_ctrl.jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(vaddrBits-1,0)), mem_br_target) & SInt(-2)).toUInt val mem_npc = (Mux(io.ctrl.mem_ctrl.jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(vaddrBits-1,0)), mem_br_target) & SInt(-2)).toUInt