From 5e009ecc758f5d17a46fd80f16352265bc0e5d6a Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 11 Jun 2015 16:08:18 -0700 Subject: [PATCH] Fix an apparently benign PC sign-extension bug --- rocket/src/main/scala/dpath.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index a60ff72f..b03d0722 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -226,7 +226,7 @@ class Datapath extends CoreModule io.fpu.dmem_resp_tag := dmem_resp_waddr io.ctrl.mem_br_taken := mem_reg_wdata(0) - val mem_br_target = mem_reg_pc + + val mem_br_target = mem_reg_pc.toSInt + Mux(io.ctrl.mem_ctrl.branch && io.ctrl.mem_br_taken, imm(IMM_SB, mem_reg_inst), Mux(io.ctrl.mem_ctrl.jal, imm(IMM_UJ, mem_reg_inst), SInt(4))) val mem_npc = (Mux(io.ctrl.mem_ctrl.jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(vaddrBits-1,0)), mem_br_target) & SInt(-2)).toUInt