tilelink: TestSRAM can emulate incompletely populated memory
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@ -9,13 +9,13 @@ import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import freechips.rocketchip.util._
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// Do not use this for synthesis! Only for simulation.
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// Do not use this for synthesis! Only for simulation.
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class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
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class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, errors: Seq[AddressSet] = Nil)(implicit p: Parameters) extends LazyModule
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{
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{
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val device = new MemoryDevice
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val device = new MemoryDevice
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val node = TLManagerNode(Seq(TLManagerPortParameters(
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val node = TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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Seq(TLManagerParameters(
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address = List(address),
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address = List(address) ++ errors,
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resources = device.reg,
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resources = device.reg,
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regionType = RegionType.UNCACHED,
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regionType = RegionType.UNCACHED,
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executable = executable,
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executable = executable,
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