diff --git a/src/main/scala/devices/tilelink/TestRAM.scala b/src/main/scala/devices/tilelink/TestRAM.scala
index d6d27edb..a64f0734 100644
--- a/src/main/scala/devices/tilelink/TestRAM.scala
+++ b/src/main/scala/devices/tilelink/TestRAM.scala
@@ -9,13 +9,13 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
 
 // Do not use this for synthesis! Only for simulation.
-class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
+class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, errors: Seq[AddressSet] = Nil)(implicit p: Parameters) extends LazyModule
 {
   val device = new MemoryDevice
 
   val node = TLManagerNode(Seq(TLManagerPortParameters(
     Seq(TLManagerParameters(
-      address            = List(address),
+      address            = List(address) ++ errors,
       resources          = device.reg,
       regionType         = RegionType.UNCACHED,
       executable         = executable,