riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink: TestSRAM can emulate incompletely populated memory

Browse Source
This commit is contained in:
Wesley W. Terpstra 2017-07-07 21:13:48 -07:00
parent 702143eb33
commit 5db0e770d5
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/devices/tilelink/TestRAM.scala
View File

@ -9,13 +9,13 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._ import freechips.rocketchip.util._
// Do not use this for synthesis! Only for simulation. // Do not use this for synthesis! Only for simulation.
class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule class TLTestRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, errors: Seq[AddressSet] = Nil)(implicit p: Parameters) extends LazyModule
{ {
val device = new MemoryDevice val device = new MemoryDevice
val node = TLManagerNode(Seq(TLManagerPortParameters( val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters( Seq(TLManagerParameters(
address = List(address), address = List(address) ++ errors,
resources = device.reg, resources = device.reg,
regionType = RegionType.UNCACHED, regionType = RegionType.UNCACHED,
executable = executable, executable = executable,