Added dramsim2 memory model to the emulator backend
This commit is contained in:
Miquel Moreto
parent
34da073077
commit
5d75ddc553
3
.gitmodules
vendored
3
.gitmodules
vendored
@ -10,3 +10,6 @@
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[submodule "uncore"]
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path = uncore
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url = git@github.com:ucb-bar/uncore.git
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[submodule "dramsim2"]
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path = dramsim2
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url = git@github.com:dramninjasUMD/DRAMSim2.git
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@ -5,7 +5,8 @@
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#include <map>
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#include "common.h"
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#include "emulator.h"
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#include "mm_emulator.cc"
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//#include "mm_emulator.cc"
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#include "mm_emulator_dramsim2.cc"
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#include "Top.h" // chisel-generated code...
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#include "disasm.h"
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@ -82,9 +83,11 @@ int main(int argc, char** argv)
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}
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// basic fixed latency memory model
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uint64_t* mem = mm_init();
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/*uint64_t* mem = mm_init();*/
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uint64_t* mm_mem = dramsim2_init();
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if (loadmem != NULL)
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load_mem(mem, loadmem);
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load_mem(mm_mem, loadmem);
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// The chisel generated code
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Top_t tile;
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@ -104,8 +107,10 @@ int main(int argc, char** argv)
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while (max_cycles == 0 || trace_count < max_cycles)
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{
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// fprintf(stderr, "trace count: %ld\n", trace_count);
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// memory model
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mm_tick_emulator (
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// mm_tick_emulator(
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dramsim2_tick_emulator (
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tile.Top__io_mem_req_cmd_valid.lo_word(),
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&tile.Top__io_mem_req_cmd_ready.values[0],
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tile.Top__io_mem_req_cmd_bits_rw.lo_word(),
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@ -120,6 +125,7 @@ int main(int argc, char** argv)
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&tile.Top__io_mem_resp_bits_tag.values[0],
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&tile.Top__io_mem_resp_bits_data.values[0]
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);
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// fprintf(stderr, "trace count: %ld (after dramsim2_tick_emulator)\n", trace_count);
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tile.Top__io_host_in_valid = LIT<1>(htif_phy.in_valid());
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tile.Top__io_host_in_bits = LIT<64>(htif_phy.in_bits());
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1
dramsim2
Submodule
1
dramsim2
Submodule
@ -0,0 +1 @@
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Subproject commit d0045b18ce34b350139a43c95c9e432f4c6e43a5
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@ -9,6 +9,10 @@ all: emulator
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CXXSRCS := emulator disasm
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CXXFLAGS := $(CXXFLAGS) -Itestbench -I$(basedir)/chisel/csrc
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DRAMSIM2_PATH := ../dramsim2/
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CXXFLAGS := $(CXXFLAGS) -I$(DRAMSIM2_PATH) -L$(DRAMSIM2_PATH) -ldramsim
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DRAMSIM2_LIB := libdramsim.so
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generated-src/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala
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cd $(basedir)/sbt && $(SBT) "project rocket" "run rocket.Top --backend c --noIoDebug --targetDir ../emulator/generated-src"
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@ -33,6 +37,9 @@ emulator: $(addsuffix .o,$(CXXSRCS)) $(MODEL).o
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emulator-debug: $(addsuffix -debug.o,$(CXXSRCS)) $(MODEL)-debug.o
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$(CXX) $(CXXFLAGS) -o $@ $^
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dramsim2:
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cd $(DRAMSIM2_PATH) ; make $(DRAMSIM2_LIB)
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all: emulator
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clean:
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@ -52,10 +59,10 @@ global_vecasm_timer_tests_vpd = $(addsuffix .vpd, $(global_vecasm_timer_tests))
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global_bmarks_vpd = $(addsuffix .vpd, $(global_bmarks))
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$(global_asm_tests_out): %.out: $(global_tstdir)/%.hex emulator
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fesvr -c -testrun -m1000000 -l +loadmem=$< none 2> $@
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fesvr -c -testrun -m2000000 -l +loadmem=$< none 2> $@
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$(global_vecasm_tests_out): %.out: $(global_tstdir)/%.hex emulator
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fesvr -c -testrun -m1000000 -l +loadmem=$< none 2> $@
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fesvr -c -testrun -m2000000 -l +loadmem=$< none 2> $@
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$(global_vecasm_timer_tests_out): %.out: $(global_tstdir)/%.hex emulator
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fesvr -c -testrun -m3000000 -l +loadmem=$< none 2> $@
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58
emulator/dramsim2_ini/DDR3_micron_64M_8B_x4_sg15.ini
Normal file
58
emulator/dramsim2_ini/DDR3_micron_64M_8B_x4_sg15.ini
Normal file
@ -0,0 +1,58 @@
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NUM_BANKS=8
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NUM_ROWS=32768
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NUM_COLS=2048
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DEVICE_WIDTH=4
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;in nanoseconds
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;#define REFRESH_PERIOD 7800
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REFRESH_PERIOD=7800
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tCK=1.5 ;*
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CL=10 ;*
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AL=0 ;*
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;AL=3; needs to be tRCD-1 or 0
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;RL=(CL+AL)
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;WL=(RL-1)
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BL=8 ;*
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tRAS=24;*
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tRCD=10 ;*
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tRRD=4 ;*
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tRC=34 ;*
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tRP=10 ;*
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tCCD=4 ;*
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tRTP=5 ;*
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tWTR=5 ;*
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tWR=10 ;*
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tRTRS=1; -- RANK PARAMETER, TODO
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tRFC=107;*
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tFAW=20;*
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tCKE=4 ;*
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tXP=4 ;*
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tCMD=1 ;*
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IDD0=100;
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IDD1=130;
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IDD2P=10;
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IDD2Q=70;
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IDD2N=70;
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IDD3Pf=60;
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IDD3Ps=60;
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IDD3N=90;
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IDD4W=255;
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IDD4R=230;
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IDD5=305;
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IDD6=9;
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IDD6L=12;
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IDD7=415;
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;same bank
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;READ_TO_PRE_DELAY=(AL+BL/2+max(tRTP,2)-2)
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;WRITE_TO_PRE_DELAY=(WL+BL/2+tWR)
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;READ_TO_WRITE_DELAY=(RL+BL/2+tRTRS-WL)
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;READ_AUTOPRE_DELAY=(AL+tRTP+tRP)
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;WRITE_AUTOPRE_DELAY=(WL+BL/2+tWR+tRP)
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;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank
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;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank
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Vdd=1.5 ; TODO: double check this
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25
emulator/dramsim2_ini/system.ini
Normal file
25
emulator/dramsim2_ini/system.ini
Normal file
@ -0,0 +1,25 @@
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; COPY THIS FILE AND MODIFY IT TO SUIT YOUR NEEDS
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NUM_CHANS=1 ; number of *logically independent* channels (i.e. each with a separate memory controller); should be a power of 2
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JEDEC_DATA_BUS_BITS=64 ; Always 64 for DDRx; if you want multiple *ganged* channels, set this to N*64
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TRANS_QUEUE_DEPTH=32 ; transaction queue, i.e., CPU-level commands such as: READ 0xbeef
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CMD_QUEUE_DEPTH=32 ; command queue, i.e., DRAM-level commands such as: CAS 544, RAS 4
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EPOCH_LENGTH=100000 ; length of an epoch in cycles (granularity of simulation)
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ROW_BUFFER_POLICY=open_page ; close_page or open_page
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ADDRESS_MAPPING_SCHEME=scheme2 ;valid schemes 1-7; For multiple independent channels, use scheme7 since it has the most parallelism
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SCHEDULING_POLICY=rank_then_bank_round_robin ; bank_then_rank_round_robin or rank_then_bank_round_robin
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QUEUING_STRUCTURE=per_rank ;per_rank or per_rank_per_bank
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;for true/false, please use all lowercase
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DEBUG_TRANS_Q=false
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DEBUG_CMD_Q=false
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DEBUG_ADDR_MAP=false
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DEBUG_BUS=false
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DEBUG_BANKSTATE=false
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DEBUG_BANKS=false
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DEBUG_POWER=false
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VIS_FILE_OUTPUT=false
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USE_LOW_POWER=true ; go into low power mode when idle?
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VERIFICATION_OUTPUT=false ; should be false for normal operation
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TOTAL_ROW_ACCESSES=4 ; maximum number of open page requests to send to the same row before forcing a row close (to prevent starvation)
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