From 5d75ddc5537551feccf4ae225326342cc79b4ba3 Mon Sep 17 00:00:00 2001 From: Miquel Moreto Date: Sun, 14 Oct 2012 14:06:28 -0700 Subject: [PATCH] Added dramsim2 memory model to the emulator backend --- .gitmodules | 3 + csrc/emulator.cc | 14 +++-- dramsim2 | 1 + emulator/Makefile | 11 +++- .../DDR3_micron_64M_8B_x4_sg15.ini | 58 +++++++++++++++++++ emulator/dramsim2_ini/system.ini | 25 ++++++++ 6 files changed, 106 insertions(+), 6 deletions(-) create mode 160000 dramsim2 create mode 100644 emulator/dramsim2_ini/DDR3_micron_64M_8B_x4_sg15.ini create mode 100644 emulator/dramsim2_ini/system.ini diff --git a/.gitmodules b/.gitmodules index 5515adc4..9cc736bb 100644 --- a/.gitmodules +++ b/.gitmodules @@ -10,3 +10,6 @@ [submodule "uncore"] path = uncore url = git@github.com:ucb-bar/uncore.git +[submodule "dramsim2"] + path = dramsim2 + url = git@github.com:dramninjasUMD/DRAMSim2.git diff --git a/csrc/emulator.cc b/csrc/emulator.cc index b6c22c4e..f0f6c9bb 100644 --- a/csrc/emulator.cc +++ b/csrc/emulator.cc @@ -5,7 +5,8 @@ #include #include "common.h" #include "emulator.h" -#include "mm_emulator.cc" +//#include "mm_emulator.cc" +#include "mm_emulator_dramsim2.cc" #include "Top.h" // chisel-generated code... #include "disasm.h" @@ -82,9 +83,11 @@ int main(int argc, char** argv) } // basic fixed latency memory model - uint64_t* mem = mm_init(); + /*uint64_t* mem = mm_init();*/ + uint64_t* mm_mem = dramsim2_init(); if (loadmem != NULL) - load_mem(mem, loadmem); + load_mem(mm_mem, loadmem); + // The chisel generated code Top_t tile; @@ -104,8 +107,10 @@ int main(int argc, char** argv) while (max_cycles == 0 || trace_count < max_cycles) { +// fprintf(stderr, "trace count: %ld\n", trace_count); // memory model - mm_tick_emulator ( +// mm_tick_emulator( + dramsim2_tick_emulator ( tile.Top__io_mem_req_cmd_valid.lo_word(), &tile.Top__io_mem_req_cmd_ready.values[0], tile.Top__io_mem_req_cmd_bits_rw.lo_word(), @@ -120,6 +125,7 @@ int main(int argc, char** argv) &tile.Top__io_mem_resp_bits_tag.values[0], &tile.Top__io_mem_resp_bits_data.values[0] ); +// fprintf(stderr, "trace count: %ld (after dramsim2_tick_emulator)\n", trace_count); tile.Top__io_host_in_valid = LIT<1>(htif_phy.in_valid()); tile.Top__io_host_in_bits = LIT<64>(htif_phy.in_bits()); diff --git a/dramsim2 b/dramsim2 new file mode 160000 index 00000000..d0045b18 --- /dev/null +++ b/dramsim2 @@ -0,0 +1 @@ +Subproject commit d0045b18ce34b350139a43c95c9e432f4c6e43a5 diff --git a/emulator/Makefile b/emulator/Makefile index 1c1d4657..1509b15f 100644 --- a/emulator/Makefile +++ b/emulator/Makefile @@ -9,6 +9,10 @@ all: emulator CXXSRCS := emulator disasm CXXFLAGS := $(CXXFLAGS) -Itestbench -I$(basedir)/chisel/csrc +DRAMSIM2_PATH := ../dramsim2/ +CXXFLAGS := $(CXXFLAGS) -I$(DRAMSIM2_PATH) -L$(DRAMSIM2_PATH) -ldramsim +DRAMSIM2_LIB := libdramsim.so + generated-src/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala cd $(basedir)/sbt && $(SBT) "project rocket" "run rocket.Top --backend c --noIoDebug --targetDir ../emulator/generated-src" @@ -33,6 +37,9 @@ emulator: $(addsuffix .o,$(CXXSRCS)) $(MODEL).o emulator-debug: $(addsuffix -debug.o,$(CXXSRCS)) $(MODEL)-debug.o $(CXX) $(CXXFLAGS) -o $@ $^ +dramsim2: + cd $(DRAMSIM2_PATH) ; make $(DRAMSIM2_LIB) + all: emulator clean: @@ -52,10 +59,10 @@ global_vecasm_timer_tests_vpd = $(addsuffix .vpd, $(global_vecasm_timer_tests)) global_bmarks_vpd = $(addsuffix .vpd, $(global_bmarks)) $(global_asm_tests_out): %.out: $(global_tstdir)/%.hex emulator - fesvr -c -testrun -m1000000 -l +loadmem=$< none 2> $@ + fesvr -c -testrun -m2000000 -l +loadmem=$< none 2> $@ $(global_vecasm_tests_out): %.out: $(global_tstdir)/%.hex emulator - fesvr -c -testrun -m1000000 -l +loadmem=$< none 2> $@ + fesvr -c -testrun -m2000000 -l +loadmem=$< none 2> $@ $(global_vecasm_timer_tests_out): %.out: $(global_tstdir)/%.hex emulator fesvr -c -testrun -m3000000 -l +loadmem=$< none 2> $@ diff --git a/emulator/dramsim2_ini/DDR3_micron_64M_8B_x4_sg15.ini b/emulator/dramsim2_ini/DDR3_micron_64M_8B_x4_sg15.ini new file mode 100644 index 00000000..8e11ebe7 --- /dev/null +++ b/emulator/dramsim2_ini/DDR3_micron_64M_8B_x4_sg15.ini @@ -0,0 +1,58 @@ +NUM_BANKS=8 +NUM_ROWS=32768 +NUM_COLS=2048 +DEVICE_WIDTH=4 + +;in nanoseconds +;#define REFRESH_PERIOD 7800 +REFRESH_PERIOD=7800 +tCK=1.5 ;* + +CL=10 ;* +AL=0 ;* +;AL=3; needs to be tRCD-1 or 0 +;RL=(CL+AL) +;WL=(RL-1) +BL=8 ;* +tRAS=24;* +tRCD=10 ;* +tRRD=4 ;* +tRC=34 ;* +tRP=10 ;* +tCCD=4 ;* +tRTP=5 ;* +tWTR=5 ;* +tWR=10 ;* +tRTRS=1; -- RANK PARAMETER, TODO +tRFC=107;* +tFAW=20;* +tCKE=4 ;* +tXP=4 ;* + +tCMD=1 ;* + +IDD0=100; +IDD1=130; +IDD2P=10; +IDD2Q=70; +IDD2N=70; +IDD3Pf=60; +IDD3Ps=60; +IDD3N=90; +IDD4W=255; +IDD4R=230; +IDD5=305; +IDD6=9; +IDD6L=12; +IDD7=415; + +;same bank +;READ_TO_PRE_DELAY=(AL+BL/2+max(tRTP,2)-2) +;WRITE_TO_PRE_DELAY=(WL+BL/2+tWR) +;READ_TO_WRITE_DELAY=(RL+BL/2+tRTRS-WL) +;READ_AUTOPRE_DELAY=(AL+tRTP+tRP) +;WRITE_AUTOPRE_DELAY=(WL+BL/2+tWR+tRP) +;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank +;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank + +Vdd=1.5 ; TODO: double check this diff --git a/emulator/dramsim2_ini/system.ini b/emulator/dramsim2_ini/system.ini new file mode 100644 index 00000000..114673af --- /dev/null +++ b/emulator/dramsim2_ini/system.ini @@ -0,0 +1,25 @@ +; COPY THIS FILE AND MODIFY IT TO SUIT YOUR NEEDS + +NUM_CHANS=1 ; number of *logically independent* channels (i.e. each with a separate memory controller); should be a power of 2 +JEDEC_DATA_BUS_BITS=64 ; Always 64 for DDRx; if you want multiple *ganged* channels, set this to N*64 +TRANS_QUEUE_DEPTH=32 ; transaction queue, i.e., CPU-level commands such as: READ 0xbeef +CMD_QUEUE_DEPTH=32 ; command queue, i.e., DRAM-level commands such as: CAS 544, RAS 4 +EPOCH_LENGTH=100000 ; length of an epoch in cycles (granularity of simulation) +ROW_BUFFER_POLICY=open_page ; close_page or open_page +ADDRESS_MAPPING_SCHEME=scheme2 ;valid schemes 1-7; For multiple independent channels, use scheme7 since it has the most parallelism +SCHEDULING_POLICY=rank_then_bank_round_robin ; bank_then_rank_round_robin or rank_then_bank_round_robin +QUEUING_STRUCTURE=per_rank ;per_rank or per_rank_per_bank + +;for true/false, please use all lowercase +DEBUG_TRANS_Q=false +DEBUG_CMD_Q=false +DEBUG_ADDR_MAP=false +DEBUG_BUS=false +DEBUG_BANKSTATE=false +DEBUG_BANKS=false +DEBUG_POWER=false +VIS_FILE_OUTPUT=false + +USE_LOW_POWER=true ; go into low power mode when idle? +VERIFICATION_OUTPUT=false ; should be false for normal operation +TOTAL_ROW_ACCESSES=4 ; maximum number of open page requests to send to the same row before forcing a row close (to prevent starvation)