riscv/rocket-chip
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all rocket-specific arbiters in one file and refactored traits slightly

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This commit is contained in:
Henry Cook
2012-10-08 13:06:45 -07:00
parent 9025d0610c
commit 5d2a470215
7 changed files with 162 additions and 146 deletions
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8
rocket/src/main/scala/tile.scala
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@ -16,9 +16,9 @@ class Tile(resetSignal: Bool = null)(implicit conf: Configuration) extends Compo
val icache = new rocketICache(128, 4) // 128 sets x 4 ways (32KB)
val dcache = new HellaCache
val arbiter = new rocketMemArbiter(2 + (if (HAVE_VEC) 1 else 0))
arbiter.io.requestor(0) <> dcache.io.mem
arbiter.io.requestor(1) <> icache.io.mem
val arbiter = new rocketMemArbiter(DMEM_PORTS)
arbiter.io.requestor(DMEM_DCACHE) <> dcache.io.mem
arbiter.io.requestor(DMEM_ICACHE) <> icache.io.mem
io.tilelink.xact_init <> arbiter.io.mem.xact_init
io.tilelink.xact_init_data <> dcache.io.mem.xact_init_data
@ -32,7 +32,7 @@ class Tile(resetSignal: Bool = null)(implicit conf: Configuration) extends Compo
if (HAVE_VEC)
{
val vicache = new rocketICache(128, 1) // 128 sets x 1 ways (8KB)
arbiter.io.requestor(2) <> vicache.io.mem
arbiter.io.requestor(DMEM_VICACHE) <> vicache.io.mem
cpu.io.vimem <> vicache.io.cpu
}