clock gate integer datapath more aggressively
This commit is contained in:
Andrew Waterman
@ -25,46 +25,42 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
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// execute definitions
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val ex_reg_pc = Reg() { UFix() };
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val ex_reg_inst = Reg() { Bits() };
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val ex_reg_raddr1 = Reg() { UFix() };
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val ex_reg_raddr2 = Reg() { UFix() };
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val ex_reg_op2 = Reg() { Bits() };
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val ex_reg_rs2 = Reg() { Bits() };
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val ex_reg_rs1 = Reg() { Bits() };
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val ex_reg_waddr = Reg() { UFix() };
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val ex_reg_ctrl_fn_dw = Reg() { UFix() };
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val ex_reg_ctrl_fn_alu = Reg() { UFix() };
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val ex_reg_sel_alu2 = Reg() { UFix() };
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val ex_reg_ctrl_sel_wb = Reg() { UFix() };
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val ex_wdata = Bits()
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val ex_reg_kill = Reg() { Bool() }
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val ex_reg_kill = Reg{Bool()}
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val ex_reg_rs1_bypass = Reg{Bool()}
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val ex_reg_rs1_lsb = Reg{Bits()}
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val ex_reg_rs1_msb = Reg{Bits()}
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val ex_reg_rs2_bypass = Reg{Bool()}
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val ex_reg_rs2_lsb = Reg{Bits()}
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val ex_reg_rs2_msb = Reg{Bits()}
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// memory definitions
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val mem_reg_pc = Reg() { UFix() };
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val mem_reg_inst = Reg() { Bits() };
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val mem_reg_rs1 = Reg() { Bits() };
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val mem_reg_rs2 = Reg() { Bits() };
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val mem_reg_waddr = Reg() { UFix() };
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val mem_reg_wdata = Reg() { Bits() };
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val mem_reg_raddr1 = Reg() { UFix() };
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val mem_reg_raddr2 = Reg() { UFix() };
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val mem_reg_kill = Reg() { Bool() }
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// writeback definitions
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val wb_reg_pc = Reg() { UFix() };
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val wb_reg_inst = Reg() { Bits() };
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val wb_reg_rs1 = Reg() { Bits() };
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val wb_reg_rs2 = Reg() { Bits() };
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val wb_reg_waddr = Reg() { UFix() }
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val wb_reg_wdata = Reg() { Bits() }
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val wb_reg_vec_waddr = Reg() { UFix() }
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val wb_reg_vec_wdata = Reg() { Bits() }
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val wb_reg_raddr1 = Reg() { UFix() };
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val wb_reg_raddr2 = Reg() { UFix() };
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val wb_reg_ll_wb = Reg(resetVal = Bool(false));
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val wb_wdata = Bits();
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val wb_wen = io.ctrl.wb_wen && io.ctrl.wb_valid || wb_reg_ll_wb
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// instruction decode stage
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val id_inst = io.imem.resp.bits.data
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val id_pc = io.imem.resp.bits.pc
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debug(id_inst)
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debug(id_pc)
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val regfile_ = Mem(31){Bits(width = 64)}
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def readRF(a: UFix) = regfile_(~a)
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@ -74,45 +70,36 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
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val id_raddr2 = id_inst(21,17).toUFix;
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// bypass muxes
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val id_rs1_dmem_bypass = id_raddr1 != UFix(0) &&
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Mux(io.ctrl.ex_wen && id_raddr1 === ex_reg_waddr, Bool(false),
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Mux(io.ctrl.mem_wen && id_raddr1 === mem_reg_waddr, io.ctrl.mem_load,
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Bool(false)))
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val id_rs1_zero = id_raddr1 === UFix(0)
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val id_rs1_ex_bypass = io.ctrl.ex_wen && id_raddr1 === ex_reg_waddr
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val id_rs1_mem_bypass = io.ctrl.mem_wen && id_raddr1 === mem_reg_waddr
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val id_rs1_bypass = id_rs1_zero || id_rs1_ex_bypass || id_rs1_mem_bypass
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val id_rs1_bypass_src = Mux(id_rs1_zero, UFix(0), Mux(id_rs1_ex_bypass, UFix(1), UFix(2) | io.ctrl.mem_load))
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val id_rs1 =
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Mux(id_raddr1 === UFix(0), UFix(0),
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Mux(io.ctrl.ex_wen && id_raddr1 === ex_reg_waddr, ex_wdata,
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Mux(io.ctrl.mem_wen && id_raddr1 === mem_reg_waddr, mem_reg_wdata,
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Mux((io.ctrl.wb_wen || wb_reg_ll_wb) && id_raddr1 === wb_reg_waddr, wb_wdata,
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readRF(id_raddr1)))))
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Mux(wb_wen && id_raddr1 === wb_reg_waddr, wb_wdata,
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readRF(id_raddr1)))
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val id_rs2_dmem_bypass = id_raddr2 != UFix(0) &&
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Mux(io.ctrl.ex_wen && id_raddr2 === ex_reg_waddr, Bool(false),
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Mux(io.ctrl.mem_wen && id_raddr2 === mem_reg_waddr, io.ctrl.mem_load,
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Bool(false)))
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val id_rs2_zero = id_raddr2 === UFix(0)
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val id_rs2_ex_bypass = io.ctrl.ex_wen && id_raddr2 === ex_reg_waddr
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val id_rs2_mem_bypass = io.ctrl.mem_wen && id_raddr2 === mem_reg_waddr
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val id_rs2_bypass = id_rs2_zero || id_rs2_ex_bypass || id_rs2_mem_bypass
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val id_rs2_bypass_src = Mux(id_rs2_zero, UFix(0), Mux(id_rs2_ex_bypass, UFix(1), UFix(2) | io.ctrl.mem_load))
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val id_rs2 = Mux(id_raddr2 === UFix(0), UFix(0),
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Mux(io.ctrl.ex_wen && id_raddr2 === ex_reg_waddr, ex_wdata,
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Mux(io.ctrl.mem_wen && id_raddr2 === mem_reg_waddr, mem_reg_wdata,
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Mux((io.ctrl.wb_wen || wb_reg_ll_wb) && id_raddr2 === wb_reg_waddr, wb_wdata,
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readRF(id_raddr2)))))
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Mux(wb_wen && id_raddr2 === wb_reg_waddr, wb_wdata,
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readRF(id_raddr2)))
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// immediate generation
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val id_imm_bj = io.ctrl.sel_alu2 === A2_BTYPE || io.ctrl.sel_alu2 === A2_JTYPE
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val id_imm_l = io.ctrl.sel_alu2 === A2_LTYPE
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val id_imm_zero = io.ctrl.sel_alu2 === A2_ZERO || io.ctrl.sel_alu2 === A2_RTYPE
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val id_imm_ibz = io.ctrl.sel_alu2 === A2_ITYPE || io.ctrl.sel_alu2 === A2_BTYPE || id_imm_zero
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val id_imm_sign = Mux(id_imm_bj, id_inst(31),
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Mux(id_imm_l, id_inst(26),
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Mux(id_imm_zero, Bits(0,1),
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id_inst(21)))) // IMM_ITYPE
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val id_imm_small = Mux(id_imm_zero, Bits(0,12),
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Cat(Mux(id_imm_bj, id_inst(31,27), id_inst(21,17)), id_inst(16,10)))
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val id_imm = Cat(Fill(32, id_imm_sign),
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Mux(id_imm_l, Cat(id_inst(26,7), Bits(0,12)),
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Mux(id_imm_ibz, Cat(Fill(20, id_imm_sign), id_imm_small),
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Cat(Fill(7, id_imm_sign), id_inst(31,7))))) // A2_JTYPE
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val id_op2_dmem_bypass = id_rs2_dmem_bypass && io.ctrl.sel_alu2 === A2_RTYPE
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val id_op2 = Mux(io.ctrl.sel_alu2 === A2_RTYPE, id_rs2, id_imm)
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def imm(sel: Bits, inst: Bits) = {
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val lsbs = Mux(sel === A2_LTYPE || sel === A2_ZERO, Bits(0),
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Mux(sel === A2_BTYPE, Cat(inst(31,27), inst(16,10)),
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Mux(sel === A2_JTYPE, inst(18,7),
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inst(21,10))))
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val msbs = Mux(sel === A2_LTYPE, inst(26,7),
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Mux(sel === A2_JTYPE, inst(31,19).toFix,
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Mux(sel === A2_ITYPE, inst(21), inst(31)).toFix))
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Cat(msbs, lsbs).toFix
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}
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io.ctrl.inst := id_inst
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io.fpu.inst := id_inst
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@ -122,21 +109,47 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
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when (!io.ctrl.killd) {
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ex_reg_pc := id_pc
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ex_reg_inst := id_inst
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ex_reg_raddr1 := id_raddr1
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ex_reg_raddr2 := id_raddr2
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ex_reg_op2 := id_op2
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ex_reg_waddr := Mux(io.ctrl.sel_wa === WA_RD, id_inst(31,27).toUFix, RA)
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ex_reg_ctrl_fn_dw := io.ctrl.fn_dw.toUFix
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ex_reg_ctrl_fn_alu := io.ctrl.fn_alu
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ex_reg_sel_alu2 := io.ctrl.sel_alu2
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ex_reg_ctrl_sel_wb := io.ctrl.sel_wb
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when (io.ctrl.ren1) { ex_reg_rs1 := id_rs1 }
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when (io.ctrl.ren2) { ex_reg_rs2 := id_rs2 }
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when (io.ctrl.ren1) {
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ex_reg_rs1_bypass := id_rs1_bypass
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ex_reg_rs1_lsb := id_rs1_bypass_src
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when (!id_rs1_bypass) {
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ex_reg_rs1_lsb := id_rs1(id_rs1_bypass_src.getWidth-1,0)
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ex_reg_rs1_msb := id_rs1(63,id_rs1_bypass_src.getWidth)
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}
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}
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when (io.ctrl.ren2) {
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ex_reg_rs2_bypass := id_rs2_bypass
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ex_reg_rs2_lsb := id_rs2_bypass_src
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when (!id_rs2_bypass) {
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ex_reg_rs2_lsb := id_rs2(id_rs2_bypass_src.getWidth-1,0)
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ex_reg_rs2_msb := id_rs2(63,id_rs2_bypass_src.getWidth)
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}
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}
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}
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val ex_raddr1 = ex_reg_inst(26,22)
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val ex_raddr2 = ex_reg_inst(21,17)
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val dmem_resp_data = if (conf.fastLoadByte) io.dmem.resp.bits.data_subword else io.dmem.resp.bits.data
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val ex_rs1 = Mux(Reg(id_rs1_dmem_bypass), dmem_resp_data, ex_reg_rs1)
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val ex_rs2 = Mux(Reg(id_rs2_dmem_bypass), dmem_resp_data, ex_reg_rs2)
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val ex_op2 = Mux(Reg(id_op2_dmem_bypass), dmem_resp_data, ex_reg_op2)
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val ex_rs1 =
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Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UFix(3), dmem_resp_data,
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Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UFix(2), wb_reg_wdata,
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Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UFix(1), mem_reg_wdata,
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Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UFix(0), Bits(0),
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Cat(ex_reg_rs1_msb, ex_reg_rs1_lsb)))))
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val ex_rs2 =
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Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UFix(3), dmem_resp_data,
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Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UFix(2), wb_reg_wdata,
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Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UFix(1), mem_reg_wdata,
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Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UFix(0), Bits(0),
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Cat(ex_reg_rs2_msb, ex_reg_rs2_lsb)))))
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val ex_imm = imm(ex_reg_sel_alu2, ex_reg_inst)
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val ex_op2 = Mux(ex_reg_sel_alu2 != A2_RTYPE, ex_imm, ex_rs2)
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val alu = new ALU
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alu.io.dw := ex_reg_ctrl_fn_dw;
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@ -149,7 +162,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
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div.io.req.valid := io.ctrl.div_val
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div.io.req.bits.fn := Cat(ex_reg_ctrl_fn_dw, io.ctrl.div_fn)
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div.io.req.bits.in0 := ex_rs1
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div.io.req.bits.in1 := ex_op2
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div.io.req.bits.in1 := ex_rs2
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div.io.req_tag := ex_reg_waddr
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div.io.req_kill := io.ctrl.div_kill
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div.io.resp_rdy := Bool(true)
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@ -168,7 +181,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
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mul_io.req.valid := io.ctrl.mul_val
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mul_io.req.bits.fn := Cat(ex_reg_ctrl_fn_dw, io.ctrl.mul_fn)
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mul_io.req.bits.in0 := ex_rs1
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mul_io.req.bits.in1 := ex_op2
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mul_io.req.bits.in1 := ex_rs2
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mul_io.req_tag := ex_reg_waddr
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mul_io.req_kill := io.ctrl.mul_kill
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mul_io.resp_rdy := Bool(true)
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@ -199,11 +212,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
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// processor control regfile read
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val pcr = new rocketDpathPCR()
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pcr.io.r.en := io.ctrl.pcr != PCR_N
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pcr.io.r.addr := wb_reg_raddr1
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pcr.io.r.addr := wb_reg_inst(26,22).toUFix
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pcr.io.host <> io.host
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pcr.io <> io.ctrl
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pcr.io.pc := wb_reg_pc
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io.ctrl.pcr_replay := pcr.io.replay
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io.ptw.ptbr := pcr.io.ptbr
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@ -211,7 +223,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
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io.ptw.status := pcr.io.status
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// branch resolution logic
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io.ctrl.jalr_eq := ex_reg_rs1 === id_pc.toFix && ex_reg_op2(id_imm_small.getWidth-1,0) === UFix(0)
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io.ctrl.jalr_eq := ex_rs1 === id_pc.toFix && ex_reg_inst(11,0) === UFix(0)
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io.ctrl.ex_br_taken :=
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Mux(io.ctrl.ex_br_type === BR_EQ, ex_rs1 === ex_rs2,
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Mux(io.ctrl.ex_br_type === BR_NE, ex_rs1 != ex_rs2,
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@ -221,21 +233,17 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
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Mux(io.ctrl.ex_br_type === BR_GEU, ex_rs1 >= ex_rs2,
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io.ctrl.ex_br_type === BR_J))))))
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val ex_pc_plus4 = ex_reg_pc + UFix(4)
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val ex_branch_target = ex_reg_pc + Cat(ex_reg_op2(VADDR_BITS-1,0), Bits(0,1)).toUFix
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val ex_pc_plus4 = ex_reg_pc + 4
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val ex_branch_target = (ex_reg_pc.toFix + (ex_imm << 1)).toUFix
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// time stamp counter
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val tsc_reg = Reg(resetVal = UFix(0,64));
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tsc_reg := tsc_reg + UFix(1);
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// instructions retired counter
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val irt_reg = Reg(resetVal = UFix(0,64));
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when (io.ctrl.wb_valid) { irt_reg := irt_reg + UFix(1); }
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val tsc_reg = WideCounter(64)
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val irt_reg = WideCounter(64, io.ctrl.wb_valid)
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// writeback select mux
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ex_wdata :=
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val ex_wdata =
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Mux(ex_reg_ctrl_sel_wb === WB_PC, ex_pc_plus4.toFix,
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Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg,
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Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg,
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Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg.value,
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Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg.value,
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alu.io.out))).toBits // WB_ALU
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// memory stage
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@ -243,11 +251,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
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when (!ex_reg_kill) {
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mem_reg_pc := ex_reg_pc
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mem_reg_inst := ex_reg_inst
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mem_reg_rs1 := ex_rs1
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mem_reg_rs2 := StoreGen(io.ctrl.ex_mem_type, Bits(0), ex_rs2).data
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mem_reg_waddr := ex_reg_waddr
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mem_reg_wdata := ex_wdata
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mem_reg_raddr1 := ex_reg_raddr1
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mem_reg_raddr2 := ex_reg_raddr2
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}
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// for load/use hazard detection (load byte/halfword)
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@ -276,6 +283,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
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io.ctrl.mem_ll_waddr := dmem_resp_waddr
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io.ctrl.mem_ll_wb := Bool(true)
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}
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when (io.ctrl.mem_ll_waddr === UFix(0)) { io.ctrl.mem_ll_wb := Bool(false) }
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io.fpu.dmem_resp_val := io.dmem.resp.valid && dmem_resp_fpu
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io.fpu.dmem_resp_data := io.dmem.resp.bits.data
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@ -286,11 +294,8 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
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when (!mem_reg_kill) {
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wb_reg_pc := mem_reg_pc
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wb_reg_inst := mem_reg_inst
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wb_reg_rs1 := mem_reg_rs1
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wb_reg_rs2 := mem_reg_rs2
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wb_reg_vec_waddr := mem_reg_waddr
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wb_reg_vec_wdata := mem_reg_wdata
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wb_reg_raddr1 := mem_reg_raddr1
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wb_reg_raddr2 := mem_reg_raddr2
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wb_reg_waddr := mem_reg_waddr
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wb_reg_wdata := Mux(io.ctrl.mem_fp_val && io.ctrl.mem_wen, io.fpu.toint_data, mem_reg_wdata)
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}
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@ -299,6 +304,9 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
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wb_reg_waddr := io.ctrl.mem_ll_waddr
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wb_reg_wdata := mem_ll_wdata
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}
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wb_wdata := Mux(io.ctrl.wb_load, io.dmem.resp.bits.data_subword,
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Mux(io.ctrl.pcr != PCR_N, pcr.io.r.data,
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wb_reg_wdata))
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if (HAVE_VEC)
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{
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@ -310,11 +318,9 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
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vec.io.valid := io.ctrl.wb_valid && pcr.io.status(SR_EV)
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vec.io.inst := wb_reg_inst
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vec.io.waddr := wb_reg_vec_waddr
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vec.io.raddr1 := wb_reg_raddr1
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vec.io.vecbank := pcr.io.vecbank
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vec.io.vecbankcnt := pcr.io.vecbankcnt
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vec.io.wdata := wb_reg_vec_wdata
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vec.io.wdata := wb_reg_wdata
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vec.io.rs2 := wb_reg_rs2
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pcr.io.vec_irq_aux := vec.io.irq_aux
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@ -322,29 +328,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
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pcr.io.vec_nxregs := vec.io.nxregs
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pcr.io.vec_nfregs := vec.io.nfregs
|
||||
|
||||
wb_wdata :=
|
||||
Mux(vec.io.wen, Cat(Bits(0,52), vec.io.appvl),
|
||||
Mux(io.ctrl.wb_load, io.dmem.resp.bits.data_subword,
|
||||
wb_reg_wdata))
|
||||
}
|
||||
else
|
||||
{
|
||||
pcr.io.vec_irq_aux := UFix(0)
|
||||
pcr.io.vec_appvl := UFix(0)
|
||||
pcr.io.vec_nxregs := UFix(0)
|
||||
pcr.io.vec_nfregs := UFix(0)
|
||||
|
||||
wb_wdata :=
|
||||
Mux(io.ctrl.wb_load, io.dmem.resp.bits.data_subword,
|
||||
wb_reg_wdata)
|
||||
when (vec.io.wen) { wb_wdata := vec.io.appvl }
|
||||
}
|
||||
|
||||
val rf_wen = io.ctrl.wb_wen || wb_reg_ll_wb
|
||||
val rf_waddr = wb_reg_waddr
|
||||
val rf_wdata = Mux(io.ctrl.wb_wen && io.ctrl.pcr != PCR_N, pcr.io.r.data, wb_wdata)
|
||||
List(rf_wen, rf_waddr, rf_wdata).map(debug _)
|
||||
when (rf_wen) { writeRF(rf_waddr, rf_wdata) }
|
||||
|
||||
when (wb_wen) { writeRF(wb_reg_waddr, wb_wdata) }
|
||||
io.ctrl.wb_waddr := wb_reg_waddr
|
||||
|
||||
// scoreboard clear (for div/mul and D$ load miss writebacks)
|
||||
@ -352,7 +339,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
|
||||
io.ctrl.fp_sboard_clra := dmem_resp_waddr
|
||||
|
||||
// processor control regfile write
|
||||
pcr.io.w.addr := wb_reg_raddr1
|
||||
pcr.io.w.addr := wb_reg_inst(26,22).toUFix
|
||||
pcr.io.w.en := io.ctrl.pcr === PCR_T || io.ctrl.pcr === PCR_S || io.ctrl.pcr === PCR_C
|
||||
pcr.io.w.data := Mux(io.ctrl.pcr === PCR_S, pcr.io.r.data | wb_reg_wdata,
|
||||
Mux(io.ctrl.pcr === PCR_C, pcr.io.r.data & ~wb_reg_wdata,
|
||||
@ -365,4 +352,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
|
||||
Mux(io.ctrl.sel_pc === PC_EX, Mux(io.ctrl.ex_jalr, ex_effective_address, ex_branch_target),
|
||||
Mux(io.ctrl.sel_pc === PC_PCR, Cat(pcr.io.evec(VADDR_BITS-1), pcr.io.evec).toUFix,
|
||||
wb_reg_pc))) // PC_WB
|
||||
|
||||
// expose debug signals to testbench
|
||||
// XXX debug() doesn't right, so create a false dependence
|
||||
val debugList = List(wb_reg_pc, wb_reg_inst, wb_wen, wb_reg_waddr, wb_wdata, wb_reg_rs1, wb_reg_rs2)
|
||||
pcr.io.pc := wb_reg_pc | (debugList.map(d => d^d).reduce(_|_)).toUFix
|
||||
debugList.foreach(debug _)
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user