diff --git a/rocket/src/main/scala/core.scala b/rocket/src/main/scala/core.scala index 60973cea..d2d677b4 100644 --- a/rocket/src/main/scala/core.scala +++ b/rocket/src/main/scala/core.scala @@ -111,7 +111,7 @@ class Core(implicit conf: RocketConfiguration) extends Component // hooking up vector memory interface dmem(2).req.valid := vu.io.dmem_req.valid dmem(2).req.bits := vu.io.dmem_req.bits - dmem(2).req.bits.data := Reg(StoreGen(vu.io.dmem_req.bits.typ, Bits(0), vu.io.dmem_req.bits.data).data) + dmem(2).req.bits.data := RegEn(StoreGen(vu.io.dmem_req.bits.typ, Bits(0), vu.io.dmem_req.bits.data).data, vu.io.dmem_req.valid && isWrite(vu.io.dmem_req.bits.cmd)) vu.io.dmem_req.ready := dmem(2).req.ready vu.io.dmem_resp.valid := dmem(2).resp.valid diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 86835d4a..c31a1dac 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -385,6 +385,7 @@ class Control(implicit conf: RocketConfiguration) extends Component val mem_reg_mem_val = Reg(resetVal = Bool(false)) val mem_reg_xcpt = Reg(resetVal = Bool(false)) val mem_reg_fp_val = Reg(resetVal = Bool(false)) + val mem_reg_vec_val = Reg(resetVal = Bool(false)) val mem_reg_replay = Reg(resetVal = Bool(false)) val mem_reg_replay_next = Reg(resetVal = Bool(false)) val mem_reg_pcr = Reg(resetVal = PCR_N) @@ -507,7 +508,7 @@ class Control(implicit conf: RocketConfiguration) extends Component ex_reg_mem_val := id_mem_val.toBool; ex_reg_valid := Bool(true) ex_reg_pcr := id_pcr - ex_reg_wen := id_wen + ex_reg_wen := id_wen && id_waddr != UFix(0) ex_reg_fp_wen := id_fp_val && io.fpu.dec.wen ex_reg_eret := id_eret.toBool; ex_reg_flush_inst := id_fence_i @@ -521,7 +522,7 @@ class Control(implicit conf: RocketConfiguration) extends Component } // replay inst in ex stage - val wb_dcache_miss = wb_reg_mem_val && (wb_reg_wen || wb_reg_fp_wen) && !io.dmem.resp.valid + val wb_dcache_miss = wb_reg_mem_val && !io.dmem.resp.valid val replay_ex = wb_dcache_miss && ex_reg_load_use || mem_reg_flush_inst || ex_reg_mem_val && !io.dmem.req.ready || ex_reg_div_val && !io.dpath.div_rdy || @@ -549,8 +550,9 @@ class Control(implicit conf: RocketConfiguration) extends Component mem_reg_eret := Bool(false); mem_reg_mem_val := Bool(false); mem_reg_flush_inst := Bool(false); - mem_reg_fp_val := Bool(false); - mem_reg_replay_next := Bool(false) + mem_reg_fp_val := Bool(false) + mem_reg_vec_val := Bool(false) + mem_reg_replay_next := Bool(false) mem_reg_xcpt := Bool(false) } .otherwise { @@ -561,9 +563,10 @@ class Control(implicit conf: RocketConfiguration) extends Component mem_reg_eret := ex_reg_eret; mem_reg_mem_val := ex_reg_mem_val; mem_reg_flush_inst := ex_reg_flush_inst; - mem_reg_fp_val := ex_reg_fp_val - mem_reg_replay_next := ex_reg_replay_next - mem_reg_mem_type := ex_reg_mem_type + mem_reg_fp_val := ex_reg_fp_val + mem_reg_vec_val := ex_reg_vec_val + mem_reg_replay_next := ex_reg_replay_next + mem_reg_mem_type := ex_reg_mem_type mem_reg_xcpt := ex_xcpt } @@ -575,7 +578,7 @@ class Control(implicit conf: RocketConfiguration) extends Component (mem_reg_mem_val && io.dmem.xcpt.pf.st, UFix(11)))) val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem - val ll_wb_kill_mem = io.dpath.mem_ll_wb && (mem_reg_wen || mem_reg_fp_wen) + val ll_wb_kill_mem = io.dpath.mem_ll_wb && (mem_reg_wen || mem_reg_fp_wen || mem_reg_vec_val || mem_reg_pcr != PCR_N) val replay_mem = ll_wb_kill_mem || mem_reg_replay || fpu_kill_mem val killm_common = ll_wb_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid ctrl_killm := killm_common || mem_xcpt || fpu_kill_mem @@ -628,12 +631,12 @@ class Control(implicit conf: RocketConfiguration) extends Component } val sboard = new Scoreboard - sboard.set(wb_reg_div_mul_val || wb_dcache_miss && io.dpath.wb_wen, io.dpath.wb_waddr) + sboard.set((wb_reg_div_mul_val || wb_dcache_miss) && io.dpath.wb_wen, io.dpath.wb_waddr) sboard.clear(io.dpath.mem_ll_wb, io.dpath.mem_ll_waddr) val id_stall_fpu = if (HAVE_FPU) { val fp_sboard = new Scoreboard - fp_sboard.set(wb_dcache_miss && wb_reg_fp_wen && !replay_wb || io.fpu.sboard_set, io.dpath.wb_waddr) + fp_sboard.set((wb_dcache_miss && wb_reg_fp_wen || io.fpu.sboard_set) && !replay_wb, io.dpath.wb_waddr) fp_sboard.clear(io.dpath.fp_sboard_clr, io.dpath.fp_sboard_clra) fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) @@ -725,7 +728,7 @@ class Control(implicit conf: RocketConfiguration) extends Component io.imem.invalidate := wb_reg_flush_inst io.dpath.mem_load := mem_reg_mem_val && mem_reg_wen - io.dpath.wb_load := wb_reg_mem_val && io.dpath.wb_wen + io.dpath.wb_load := wb_reg_mem_val && wb_reg_wen io.dpath.ren2 := id_renx2.toBool; io.dpath.ren1 := id_renx1.toBool; io.dpath.sel_alu2 := id_sel_alu2.toUFix diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index 3979bef0..ce2d3c80 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -25,46 +25,42 @@ class Datapath(implicit conf: RocketConfiguration) extends Component // execute definitions val ex_reg_pc = Reg() { UFix() }; val ex_reg_inst = Reg() { Bits() }; - val ex_reg_raddr1 = Reg() { UFix() }; - val ex_reg_raddr2 = Reg() { UFix() }; - val ex_reg_op2 = Reg() { Bits() }; - val ex_reg_rs2 = Reg() { Bits() }; - val ex_reg_rs1 = Reg() { Bits() }; val ex_reg_waddr = Reg() { UFix() }; val ex_reg_ctrl_fn_dw = Reg() { UFix() }; val ex_reg_ctrl_fn_alu = Reg() { UFix() }; + val ex_reg_sel_alu2 = Reg() { UFix() }; val ex_reg_ctrl_sel_wb = Reg() { UFix() }; - val ex_wdata = Bits() - val ex_reg_kill = Reg() { Bool() } + val ex_reg_kill = Reg{Bool()} + val ex_reg_rs1_bypass = Reg{Bool()} + val ex_reg_rs1_lsb = Reg{Bits()} + val ex_reg_rs1_msb = Reg{Bits()} + val ex_reg_rs2_bypass = Reg{Bool()} + val ex_reg_rs2_lsb = Reg{Bits()} + val ex_reg_rs2_msb = Reg{Bits()} // memory definitions val mem_reg_pc = Reg() { UFix() }; val mem_reg_inst = Reg() { Bits() }; + val mem_reg_rs1 = Reg() { Bits() }; val mem_reg_rs2 = Reg() { Bits() }; val mem_reg_waddr = Reg() { UFix() }; val mem_reg_wdata = Reg() { Bits() }; - val mem_reg_raddr1 = Reg() { UFix() }; - val mem_reg_raddr2 = Reg() { UFix() }; val mem_reg_kill = Reg() { Bool() } // writeback definitions val wb_reg_pc = Reg() { UFix() }; val wb_reg_inst = Reg() { Bits() }; + val wb_reg_rs1 = Reg() { Bits() }; val wb_reg_rs2 = Reg() { Bits() }; val wb_reg_waddr = Reg() { UFix() } val wb_reg_wdata = Reg() { Bits() } - val wb_reg_vec_waddr = Reg() { UFix() } - val wb_reg_vec_wdata = Reg() { Bits() } - val wb_reg_raddr1 = Reg() { UFix() }; - val wb_reg_raddr2 = Reg() { UFix() }; val wb_reg_ll_wb = Reg(resetVal = Bool(false)); val wb_wdata = Bits(); + val wb_wen = io.ctrl.wb_wen && io.ctrl.wb_valid || wb_reg_ll_wb // instruction decode stage val id_inst = io.imem.resp.bits.data val id_pc = io.imem.resp.bits.pc - debug(id_inst) - debug(id_pc) val regfile_ = Mem(31){Bits(width = 64)} def readRF(a: UFix) = regfile_(~a) @@ -74,45 +70,36 @@ class Datapath(implicit conf: RocketConfiguration) extends Component val id_raddr2 = id_inst(21,17).toUFix; // bypass muxes - val id_rs1_dmem_bypass = id_raddr1 != UFix(0) && - Mux(io.ctrl.ex_wen && id_raddr1 === ex_reg_waddr, Bool(false), - Mux(io.ctrl.mem_wen && id_raddr1 === mem_reg_waddr, io.ctrl.mem_load, - Bool(false))) + val id_rs1_zero = id_raddr1 === UFix(0) + val id_rs1_ex_bypass = io.ctrl.ex_wen && id_raddr1 === ex_reg_waddr + val id_rs1_mem_bypass = io.ctrl.mem_wen && id_raddr1 === mem_reg_waddr + val id_rs1_bypass = id_rs1_zero || id_rs1_ex_bypass || id_rs1_mem_bypass + val id_rs1_bypass_src = Mux(id_rs1_zero, UFix(0), Mux(id_rs1_ex_bypass, UFix(1), UFix(2) | io.ctrl.mem_load)) val id_rs1 = Mux(id_raddr1 === UFix(0), UFix(0), - Mux(io.ctrl.ex_wen && id_raddr1 === ex_reg_waddr, ex_wdata, - Mux(io.ctrl.mem_wen && id_raddr1 === mem_reg_waddr, mem_reg_wdata, - Mux((io.ctrl.wb_wen || wb_reg_ll_wb) && id_raddr1 === wb_reg_waddr, wb_wdata, - readRF(id_raddr1))))) + Mux(wb_wen && id_raddr1 === wb_reg_waddr, wb_wdata, + readRF(id_raddr1))) - val id_rs2_dmem_bypass = id_raddr2 != UFix(0) && - Mux(io.ctrl.ex_wen && id_raddr2 === ex_reg_waddr, Bool(false), - Mux(io.ctrl.mem_wen && id_raddr2 === mem_reg_waddr, io.ctrl.mem_load, - Bool(false))) + val id_rs2_zero = id_raddr2 === UFix(0) + val id_rs2_ex_bypass = io.ctrl.ex_wen && id_raddr2 === ex_reg_waddr + val id_rs2_mem_bypass = io.ctrl.mem_wen && id_raddr2 === mem_reg_waddr + val id_rs2_bypass = id_rs2_zero || id_rs2_ex_bypass || id_rs2_mem_bypass + val id_rs2_bypass_src = Mux(id_rs2_zero, UFix(0), Mux(id_rs2_ex_bypass, UFix(1), UFix(2) | io.ctrl.mem_load)) val id_rs2 = Mux(id_raddr2 === UFix(0), UFix(0), - Mux(io.ctrl.ex_wen && id_raddr2 === ex_reg_waddr, ex_wdata, - Mux(io.ctrl.mem_wen && id_raddr2 === mem_reg_waddr, mem_reg_wdata, - Mux((io.ctrl.wb_wen || wb_reg_ll_wb) && id_raddr2 === wb_reg_waddr, wb_wdata, - readRF(id_raddr2))))) + Mux(wb_wen && id_raddr2 === wb_reg_waddr, wb_wdata, + readRF(id_raddr2))) // immediate generation - val id_imm_bj = io.ctrl.sel_alu2 === A2_BTYPE || io.ctrl.sel_alu2 === A2_JTYPE - val id_imm_l = io.ctrl.sel_alu2 === A2_LTYPE - val id_imm_zero = io.ctrl.sel_alu2 === A2_ZERO || io.ctrl.sel_alu2 === A2_RTYPE - val id_imm_ibz = io.ctrl.sel_alu2 === A2_ITYPE || io.ctrl.sel_alu2 === A2_BTYPE || id_imm_zero - val id_imm_sign = Mux(id_imm_bj, id_inst(31), - Mux(id_imm_l, id_inst(26), - Mux(id_imm_zero, Bits(0,1), - id_inst(21)))) // IMM_ITYPE - val id_imm_small = Mux(id_imm_zero, Bits(0,12), - Cat(Mux(id_imm_bj, id_inst(31,27), id_inst(21,17)), id_inst(16,10))) - val id_imm = Cat(Fill(32, id_imm_sign), - Mux(id_imm_l, Cat(id_inst(26,7), Bits(0,12)), - Mux(id_imm_ibz, Cat(Fill(20, id_imm_sign), id_imm_small), - Cat(Fill(7, id_imm_sign), id_inst(31,7))))) // A2_JTYPE - - val id_op2_dmem_bypass = id_rs2_dmem_bypass && io.ctrl.sel_alu2 === A2_RTYPE - val id_op2 = Mux(io.ctrl.sel_alu2 === A2_RTYPE, id_rs2, id_imm) + def imm(sel: Bits, inst: Bits) = { + val lsbs = Mux(sel === A2_LTYPE || sel === A2_ZERO, Bits(0), + Mux(sel === A2_BTYPE, Cat(inst(31,27), inst(16,10)), + Mux(sel === A2_JTYPE, inst(18,7), + inst(21,10)))) + val msbs = Mux(sel === A2_LTYPE, inst(26,7), + Mux(sel === A2_JTYPE, inst(31,19).toFix, + Mux(sel === A2_ITYPE, inst(21), inst(31)).toFix)) + Cat(msbs, lsbs).toFix + } io.ctrl.inst := id_inst io.fpu.inst := id_inst @@ -122,21 +109,47 @@ class Datapath(implicit conf: RocketConfiguration) extends Component when (!io.ctrl.killd) { ex_reg_pc := id_pc ex_reg_inst := id_inst - ex_reg_raddr1 := id_raddr1 - ex_reg_raddr2 := id_raddr2 - ex_reg_op2 := id_op2 ex_reg_waddr := Mux(io.ctrl.sel_wa === WA_RD, id_inst(31,27).toUFix, RA) ex_reg_ctrl_fn_dw := io.ctrl.fn_dw.toUFix ex_reg_ctrl_fn_alu := io.ctrl.fn_alu + ex_reg_sel_alu2 := io.ctrl.sel_alu2 ex_reg_ctrl_sel_wb := io.ctrl.sel_wb - when (io.ctrl.ren1) { ex_reg_rs1 := id_rs1 } - when (io.ctrl.ren2) { ex_reg_rs2 := id_rs2 } + when (io.ctrl.ren1) { + ex_reg_rs1_bypass := id_rs1_bypass + ex_reg_rs1_lsb := id_rs1_bypass_src + when (!id_rs1_bypass) { + ex_reg_rs1_lsb := id_rs1(id_rs1_bypass_src.getWidth-1,0) + ex_reg_rs1_msb := id_rs1(63,id_rs1_bypass_src.getWidth) + } + } + when (io.ctrl.ren2) { + ex_reg_rs2_bypass := id_rs2_bypass + ex_reg_rs2_lsb := id_rs2_bypass_src + when (!id_rs2_bypass) { + ex_reg_rs2_lsb := id_rs2(id_rs2_bypass_src.getWidth-1,0) + ex_reg_rs2_msb := id_rs2(63,id_rs2_bypass_src.getWidth) + } + } } + val ex_raddr1 = ex_reg_inst(26,22) + val ex_raddr2 = ex_reg_inst(21,17) + val dmem_resp_data = if (conf.fastLoadByte) io.dmem.resp.bits.data_subword else io.dmem.resp.bits.data - val ex_rs1 = Mux(Reg(id_rs1_dmem_bypass), dmem_resp_data, ex_reg_rs1) - val ex_rs2 = Mux(Reg(id_rs2_dmem_bypass), dmem_resp_data, ex_reg_rs2) - val ex_op2 = Mux(Reg(id_op2_dmem_bypass), dmem_resp_data, ex_reg_op2) + val ex_rs1 = + Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UFix(3), dmem_resp_data, + Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UFix(2), wb_reg_wdata, + Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UFix(1), mem_reg_wdata, + Mux(ex_reg_rs1_bypass && ex_reg_rs1_lsb === UFix(0), Bits(0), + Cat(ex_reg_rs1_msb, ex_reg_rs1_lsb))))) + val ex_rs2 = + Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UFix(3), dmem_resp_data, + Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UFix(2), wb_reg_wdata, + Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UFix(1), mem_reg_wdata, + Mux(ex_reg_rs2_bypass && ex_reg_rs2_lsb === UFix(0), Bits(0), + Cat(ex_reg_rs2_msb, ex_reg_rs2_lsb))))) + val ex_imm = imm(ex_reg_sel_alu2, ex_reg_inst) + val ex_op2 = Mux(ex_reg_sel_alu2 != A2_RTYPE, ex_imm, ex_rs2) val alu = new ALU alu.io.dw := ex_reg_ctrl_fn_dw; @@ -149,7 +162,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component div.io.req.valid := io.ctrl.div_val div.io.req.bits.fn := Cat(ex_reg_ctrl_fn_dw, io.ctrl.div_fn) div.io.req.bits.in0 := ex_rs1 - div.io.req.bits.in1 := ex_op2 + div.io.req.bits.in1 := ex_rs2 div.io.req_tag := ex_reg_waddr div.io.req_kill := io.ctrl.div_kill div.io.resp_rdy := Bool(true) @@ -168,7 +181,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component mul_io.req.valid := io.ctrl.mul_val mul_io.req.bits.fn := Cat(ex_reg_ctrl_fn_dw, io.ctrl.mul_fn) mul_io.req.bits.in0 := ex_rs1 - mul_io.req.bits.in1 := ex_op2 + mul_io.req.bits.in1 := ex_rs2 mul_io.req_tag := ex_reg_waddr mul_io.req_kill := io.ctrl.mul_kill mul_io.resp_rdy := Bool(true) @@ -199,11 +212,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Component // processor control regfile read val pcr = new rocketDpathPCR() pcr.io.r.en := io.ctrl.pcr != PCR_N - pcr.io.r.addr := wb_reg_raddr1 + pcr.io.r.addr := wb_reg_inst(26,22).toUFix pcr.io.host <> io.host pcr.io <> io.ctrl - pcr.io.pc := wb_reg_pc io.ctrl.pcr_replay := pcr.io.replay io.ptw.ptbr := pcr.io.ptbr @@ -211,7 +223,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component io.ptw.status := pcr.io.status // branch resolution logic - io.ctrl.jalr_eq := ex_reg_rs1 === id_pc.toFix && ex_reg_op2(id_imm_small.getWidth-1,0) === UFix(0) + io.ctrl.jalr_eq := ex_rs1 === id_pc.toFix && ex_reg_inst(11,0) === UFix(0) io.ctrl.ex_br_taken := Mux(io.ctrl.ex_br_type === BR_EQ, ex_rs1 === ex_rs2, Mux(io.ctrl.ex_br_type === BR_NE, ex_rs1 != ex_rs2, @@ -221,21 +233,17 @@ class Datapath(implicit conf: RocketConfiguration) extends Component Mux(io.ctrl.ex_br_type === BR_GEU, ex_rs1 >= ex_rs2, io.ctrl.ex_br_type === BR_J)))))) - val ex_pc_plus4 = ex_reg_pc + UFix(4) - val ex_branch_target = ex_reg_pc + Cat(ex_reg_op2(VADDR_BITS-1,0), Bits(0,1)).toUFix + val ex_pc_plus4 = ex_reg_pc + 4 + val ex_branch_target = (ex_reg_pc.toFix + (ex_imm << 1)).toUFix - // time stamp counter - val tsc_reg = Reg(resetVal = UFix(0,64)); - tsc_reg := tsc_reg + UFix(1); - // instructions retired counter - val irt_reg = Reg(resetVal = UFix(0,64)); - when (io.ctrl.wb_valid) { irt_reg := irt_reg + UFix(1); } + val tsc_reg = WideCounter(64) + val irt_reg = WideCounter(64, io.ctrl.wb_valid) // writeback select mux - ex_wdata := + val ex_wdata = Mux(ex_reg_ctrl_sel_wb === WB_PC, ex_pc_plus4.toFix, - Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg, - Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg, + Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg.value, + Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg.value, alu.io.out))).toBits // WB_ALU // memory stage @@ -243,11 +251,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Component when (!ex_reg_kill) { mem_reg_pc := ex_reg_pc mem_reg_inst := ex_reg_inst + mem_reg_rs1 := ex_rs1 mem_reg_rs2 := StoreGen(io.ctrl.ex_mem_type, Bits(0), ex_rs2).data mem_reg_waddr := ex_reg_waddr mem_reg_wdata := ex_wdata - mem_reg_raddr1 := ex_reg_raddr1 - mem_reg_raddr2 := ex_reg_raddr2 } // for load/use hazard detection (load byte/halfword) @@ -276,6 +283,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component io.ctrl.mem_ll_waddr := dmem_resp_waddr io.ctrl.mem_ll_wb := Bool(true) } + when (io.ctrl.mem_ll_waddr === UFix(0)) { io.ctrl.mem_ll_wb := Bool(false) } io.fpu.dmem_resp_val := io.dmem.resp.valid && dmem_resp_fpu io.fpu.dmem_resp_data := io.dmem.resp.bits.data @@ -286,11 +294,8 @@ class Datapath(implicit conf: RocketConfiguration) extends Component when (!mem_reg_kill) { wb_reg_pc := mem_reg_pc wb_reg_inst := mem_reg_inst + wb_reg_rs1 := mem_reg_rs1 wb_reg_rs2 := mem_reg_rs2 - wb_reg_vec_waddr := mem_reg_waddr - wb_reg_vec_wdata := mem_reg_wdata - wb_reg_raddr1 := mem_reg_raddr1 - wb_reg_raddr2 := mem_reg_raddr2 wb_reg_waddr := mem_reg_waddr wb_reg_wdata := Mux(io.ctrl.mem_fp_val && io.ctrl.mem_wen, io.fpu.toint_data, mem_reg_wdata) } @@ -299,6 +304,9 @@ class Datapath(implicit conf: RocketConfiguration) extends Component wb_reg_waddr := io.ctrl.mem_ll_waddr wb_reg_wdata := mem_ll_wdata } + wb_wdata := Mux(io.ctrl.wb_load, io.dmem.resp.bits.data_subword, + Mux(io.ctrl.pcr != PCR_N, pcr.io.r.data, + wb_reg_wdata)) if (HAVE_VEC) { @@ -310,11 +318,9 @@ class Datapath(implicit conf: RocketConfiguration) extends Component vec.io.valid := io.ctrl.wb_valid && pcr.io.status(SR_EV) vec.io.inst := wb_reg_inst - vec.io.waddr := wb_reg_vec_waddr - vec.io.raddr1 := wb_reg_raddr1 vec.io.vecbank := pcr.io.vecbank vec.io.vecbankcnt := pcr.io.vecbankcnt - vec.io.wdata := wb_reg_vec_wdata + vec.io.wdata := wb_reg_wdata vec.io.rs2 := wb_reg_rs2 pcr.io.vec_irq_aux := vec.io.irq_aux @@ -322,29 +328,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Component pcr.io.vec_nxregs := vec.io.nxregs pcr.io.vec_nfregs := vec.io.nfregs - wb_wdata := - Mux(vec.io.wen, Cat(Bits(0,52), vec.io.appvl), - Mux(io.ctrl.wb_load, io.dmem.resp.bits.data_subword, - wb_reg_wdata)) - } - else - { - pcr.io.vec_irq_aux := UFix(0) - pcr.io.vec_appvl := UFix(0) - pcr.io.vec_nxregs := UFix(0) - pcr.io.vec_nfregs := UFix(0) - - wb_wdata := - Mux(io.ctrl.wb_load, io.dmem.resp.bits.data_subword, - wb_reg_wdata) + when (vec.io.wen) { wb_wdata := vec.io.appvl } } - val rf_wen = io.ctrl.wb_wen || wb_reg_ll_wb - val rf_waddr = wb_reg_waddr - val rf_wdata = Mux(io.ctrl.wb_wen && io.ctrl.pcr != PCR_N, pcr.io.r.data, wb_wdata) - List(rf_wen, rf_waddr, rf_wdata).map(debug _) - when (rf_wen) { writeRF(rf_waddr, rf_wdata) } - + when (wb_wen) { writeRF(wb_reg_waddr, wb_wdata) } io.ctrl.wb_waddr := wb_reg_waddr // scoreboard clear (for div/mul and D$ load miss writebacks) @@ -352,7 +339,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Component io.ctrl.fp_sboard_clra := dmem_resp_waddr // processor control regfile write - pcr.io.w.addr := wb_reg_raddr1 + pcr.io.w.addr := wb_reg_inst(26,22).toUFix pcr.io.w.en := io.ctrl.pcr === PCR_T || io.ctrl.pcr === PCR_S || io.ctrl.pcr === PCR_C pcr.io.w.data := Mux(io.ctrl.pcr === PCR_S, pcr.io.r.data | wb_reg_wdata, Mux(io.ctrl.pcr === PCR_C, pcr.io.r.data & ~wb_reg_wdata, @@ -365,4 +352,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Component Mux(io.ctrl.sel_pc === PC_EX, Mux(io.ctrl.ex_jalr, ex_effective_address, ex_branch_target), Mux(io.ctrl.sel_pc === PC_PCR, Cat(pcr.io.evec(VADDR_BITS-1), pcr.io.evec).toUFix, wb_reg_pc))) // PC_WB + + // expose debug signals to testbench + // XXX debug() doesn't right, so create a false dependence + val debugList = List(wb_reg_pc, wb_reg_inst, wb_wen, wb_reg_waddr, wb_wdata, wb_reg_rs1, wb_reg_rs2) + pcr.io.pc := wb_reg_pc | (debugList.map(d => d^d).reduce(_|_)).toUFix + debugList.foreach(debug _) } diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index f12a685a..3dc911be 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -4,6 +4,7 @@ import Chisel._ import Node._ import Constants._ import scala.math._ +import Util._ class ioDpathBTB extends Bundle() { @@ -86,10 +87,10 @@ class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component { val io = new ioDpathPCR - val reg_epc = Reg() { UFix() }; - val reg_badvaddr = Reg() { UFix() }; - val reg_ebase = Reg() { UFix() }; - val reg_count = Reg() { UFix() }; + val reg_epc = Reg{Fix()} + val reg_badvaddr = Reg{Fix()} + val reg_ebase = Reg{Fix()} + val reg_count = WideCounter(32) val reg_compare = Reg() { UFix() }; val reg_cause = Reg() { Bits() }; val reg_tohost = Reg(resetVal = Bits(0, 64)); @@ -128,7 +129,7 @@ class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component io.ptbr_wen := reg_status_vm.toBool && wen && (waddr === PCR_PTBR); io.status := Cat(reg_status_im, Bits(0,7), reg_status_vm, reg_status_sx, reg_status_ux, reg_status_s, reg_status_ps, reg_status_ec, reg_status_ev, reg_status_ef, reg_status_et); - io.evec := Mux(io.exception, reg_ebase, reg_epc) + io.evec := Mux(io.exception, reg_ebase, reg_epc).toUFix io.ptbr := reg_ptbr; io.host.debug.error_mode := reg_error_mode; io.r.data := rdata; @@ -168,7 +169,6 @@ class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component when (reg_count === reg_compare) { r_irq_timer := Bool(true); } - reg_count := reg_count + UFix(1); io.irq_timer := r_irq_timer; io.irq_ipi := r_irq_ipi; @@ -191,9 +191,9 @@ class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component reg_status_ec := Bool(HAVE_RVC) && wdata(SR_EC).toBool; reg_status_et := wdata(SR_ET).toBool; } - when (waddr === PCR_EPC) { reg_epc := wdata(VADDR_BITS,0).toUFix; } + when (waddr === PCR_EPC) { reg_epc := wdata(VADDR_BITS,0).toFix } when (waddr === PCR_EVEC) { reg_ebase := wdata(VADDR_BITS-1,0).toUFix; } - when (waddr === PCR_COUNT) { reg_count := wdata(31,0).toUFix; } + when (waddr === PCR_COUNT) { reg_count := wdata.toUFix } when (waddr === PCR_COMPARE) { reg_compare := wdata(31,0).toUFix; r_irq_timer := Bool(false); } when (waddr === PCR_COREID) { reg_coreid := wdata(15,0) } when (waddr === PCR_FROMHOST) { when (reg_fromhost === UFix(0) || io.w.en) { reg_fromhost := wdata } } @@ -210,19 +210,19 @@ class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component rdata := io.status // raddr === PCR_STATUS switch (raddr) { - is (PCR_EPC) { rdata := Cat(Fill(64-VADDR_BITS-1, reg_epc(VADDR_BITS)), reg_epc); } - is (PCR_BADVADDR) { rdata := Cat(Fill(64-VADDR_BITS-1, reg_badvaddr(VADDR_BITS)), reg_badvaddr); } - is (PCR_EVEC) { rdata := Cat(Fill(64-VADDR_BITS, reg_ebase(VADDR_BITS-1)), reg_ebase); } - is (PCR_COUNT) { rdata := Cat(Fill(32, reg_count(31)), reg_count); } - is (PCR_COMPARE) { rdata := Cat(Fill(32, reg_compare(31)), reg_compare); } - is (PCR_CAUSE) { rdata := Cat(reg_cause(5), Bits(0,58), reg_cause(4,0)); } + is (PCR_EPC) { rdata := reg_epc } + is (PCR_BADVADDR) { rdata := reg_badvaddr } + is (PCR_EVEC) { rdata := reg_ebase } + is (PCR_COUNT) { rdata := reg_count } + is (PCR_COMPARE) { rdata := reg_compare } + is (PCR_CAUSE) { rdata := reg_cause(5) << 63 | reg_cause(4,0) } is (PCR_COREID) { rdata := reg_coreid } is (PCR_IMPL) { rdata := Bits(2) } is (PCR_FROMHOST) { rdata := reg_fromhost; } is (PCR_TOHOST) { rdata := reg_tohost; } is (PCR_K0) { rdata := reg_k0; } is (PCR_K1) { rdata := reg_k1; } - is (PCR_PTBR) { rdata := Cat(Bits(0,64-PADDR_BITS), reg_ptbr); } + is (PCR_PTBR) { rdata := reg_ptbr } is (PCR_VECBANK) { rdata := Cat(Bits(0, 56), reg_vecbank) } is (PCR_VECCFG) { rdata := Cat(Bits(0, 40), io.vec_nfregs, io.vec_nxregs, io.vec_appvl) } } diff --git a/rocket/src/main/scala/dpath_vec.scala b/rocket/src/main/scala/dpath_vec.scala index 6bf6a8b1..7d922813 100644 --- a/rocket/src/main/scala/dpath_vec.scala +++ b/rocket/src/main/scala/dpath_vec.scala @@ -28,8 +28,6 @@ class ioDpathVec extends Bundle val iface = new ioDpathVecInterface() val valid = Bool(INPUT) val inst = Bits(INPUT, 32) - val waddr = UFix(INPUT, 5) - val raddr1 = UFix(INPUT, 5) val vecbank = Bits(INPUT, 8) val vecbankcnt = UFix(INPUT, 4) val wdata = Bits(INPUT, 64) @@ -151,14 +149,16 @@ class rocketDpathVec extends Component io.nfregs := reg_nfregs val appvlm1 = appvl - UFix(1) + val waddr = io.inst(31,27) + val raddr1 = io.inst(26,22) io.iface.vcmdq.bits := Mux(io.ctrl.sel_vcmd === VCMD_I, Cat(Bits(0,2), Bits(0,4), io.inst(9,8), Bits(0,6), Bits(0,6)), Mux(io.ctrl.sel_vcmd === VCMD_F, Cat(Bits(0,2), Bits(1,3), io.inst(9,7), Bits(0,6), Bits(0,6)), - Mux(io.ctrl.sel_vcmd === VCMD_TX, Cat(Bits(1,2), io.inst(13,8), Bits(0,1), io.waddr, Bits(0,1), io.raddr1), - Mux(io.ctrl.sel_vcmd === VCMD_TF, Cat(Bits(1,2), io.inst(13,8), Bits(1,1), io.waddr, Bits(1,1), io.raddr1), - Mux(io.ctrl.sel_vcmd === VCMD_MX, Cat(Bits(1,1), io.inst(13,12), io.inst(2), io.inst(10,7), Bits(0,1), io.waddr, Bits(0,1), io.waddr), - Mux(io.ctrl.sel_vcmd === VCMD_MF, Cat(Bits(1,1), io.inst(13,12), io.inst(2), io.inst(10,7), Bits(1,1), io.waddr, Bits(1,1), io.waddr), + Mux(io.ctrl.sel_vcmd === VCMD_TX, Cat(Bits(1,2), io.inst(13,8), Bits(0,1), waddr, Bits(0,1), raddr1), + Mux(io.ctrl.sel_vcmd === VCMD_TF, Cat(Bits(1,2), io.inst(13,8), Bits(1,1), waddr, Bits(1,1), raddr1), + Mux(io.ctrl.sel_vcmd === VCMD_MX, Cat(Bits(1,1), io.inst(13,12), io.inst(2), io.inst(10,7), Bits(0,1), waddr, Bits(0,1), waddr), + Mux(io.ctrl.sel_vcmd === VCMD_MF, Cat(Bits(1,1), io.inst(13,12), io.inst(2), io.inst(10,7), Bits(1,1), waddr, Bits(1,1), waddr), Mux(io.ctrl.sel_vcmd === VCMD_A, io.wdata(SZ_VCMD-1, 0), Bits(0,20)))))))) diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala index 3b11ffd6..bd747109 100644 --- a/rocket/src/main/scala/util.scala +++ b/rocket/src/main/scala/util.scala @@ -7,4 +7,30 @@ object Util implicit def intToUFix(x: Int): UFix = UFix(x) implicit def intToBoolean(x: Int): Boolean = if (x != 0) true else false implicit def booleanToInt(x: Boolean): Int = if (x) 1 else 0 + + implicit def wcToUFix(c: WideCounter): UFix = c.value +} + +// a counter that clock gates most of its MSBs using the LSB carry-out +case class WideCounter(width: Int, inc: Bool = Bool(true)) +{ + private val isWide = width >= 4 + private val smallWidth = if (isWide) log2Up(width) else width + private val small = Reg(resetVal = UFix(0, smallWidth)) + private val nextSmall = small + UFix(1, smallWidth+1) + when (inc) { small := nextSmall(smallWidth-1,0) } + + private val large = if (isWide) { + val r = Reg(resetVal = UFix(0, width - smallWidth)) + when (inc && nextSmall(smallWidth)) { r := r + UFix(1) } + r + } else null + + val value = Cat(large, small) + + def := (x: UFix) = { + val w = x.getWidth + small := x(w.min(smallWidth)-1,0) + if (isWide) large := (if (w < smallWidth) UFix(0) else x(w.min(width)-1,smallWidth)) + } }