riscv/rocket-chip
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clock gate integer datapath more aggressively

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Andrew Waterman committed 2012-11-17 06:48:44 -08:00
1 parent cc067026a2
commit 5a7777fe4d
6 files changed
+158 -136
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rocket/src/main/scala/core.scala
+1 -1
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@@ -111,7 +111,7 @@ class Core(implicit conf: RocketConfiguration) extends Component
// hooking up vector memory interface
dmem(2).req.valid := vu.io.dmem_req.valid
dmem(2).req.bits := vu.io.dmem_req.bits
dmem(2).req.bits.data := Reg(StoreGen(vu.io.dmem_req.bits.typ, Bits(0), vu.io.dmem_req.bits.data).data)
dmem(2).req.bits.data := RegEn(StoreGen(vu.io.dmem_req.bits.typ, Bits(0), vu.io.dmem_req.bits.data).data, vu.io.dmem_req.valid && isWrite(vu.io.dmem_req.bits.cmd))
vu.io.dmem_req.ready := dmem(2).req.ready
vu.io.dmem_resp.valid := dmem(2).resp.valid