From 7971947d6c19f79c01c84164ca6ae788ac8ddf8c Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sun, 19 Mar 2017 16:34:23 -0700 Subject: [PATCH 1/3] tilelink2 Monitor: don't inspect bits if valid is forbidden --- src/main/scala/uncore/tilelink2/Monitor.scala | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/Monitor.scala b/src/main/scala/uncore/tilelink2/Monitor.scala index e540f00a..87ea1931 100644 --- a/src/main/scala/uncore/tilelink2/Monitor.scala +++ b/src/main/scala/uncore/tilelink2/Monitor.scala @@ -295,10 +295,16 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args) def legalizeFormat(bundle: TLBundleSnoop, edge: TLEdge)(implicit sourceInfo: SourceInfo) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } - when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } - when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } - when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } + if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { + when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } + when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } + when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } + } else { + assert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) + assert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) + assert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) + } } def legalizeMultibeatA(a: DecoupledSnoop[TLBundleA], edge: TLEdge)(implicit sourceInfo: SourceInfo) { @@ -398,9 +404,11 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args) def legalizeMultibeat(bundle: TLBundleSnoop, edge: TLEdge)(implicit sourceInfo: SourceInfo) { legalizeMultibeatA(bundle.a, edge) - legalizeMultibeatB(bundle.b, edge) - legalizeMultibeatC(bundle.c, edge) legalizeMultibeatD(bundle.d, edge) + if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { + legalizeMultibeatB(bundle.b, edge) + legalizeMultibeatC(bundle.c, edge) + } } def legalizeSourceUnique(bundle: TLBundleSnoop, edge: TLEdge)(implicit sourceInfo: SourceInfo) { From c9459fe4eb6b49af76a48f9e7b0dd032e71d8bdf Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sun, 19 Mar 2017 17:02:24 -0700 Subject: [PATCH 2/3] tilelink2 Xbar: don't use unnecessary ports --- src/main/scala/uncore/tilelink2/Xbar.scala | 44 +++++++++++++++++----- 1 file changed, 35 insertions(+), 9 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/Xbar.scala b/src/main/scala/uncore/tilelink2/Xbar.scala index f7cc2e62..6c43e849 100644 --- a/src/main/scala/uncore/tilelink2/Xbar.scala +++ b/src/main/scala/uncore/tilelink2/Xbar.scala @@ -103,24 +103,50 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst)(implicit p: val in = Wire(Vec(io.in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) - in(i) <> io.in(i) - // prefix sources + + in(i).a <> io.in(i).a + io.in(i).d <> in(i).d in(i).a.bits.source := io.in(i).a.bits.source | UInt(r.start) - in(i).c.bits.source := io.in(i).c.bits.source | UInt(r.start) - // defix sources - io.in(i).b.bits.source := trim(in(i).b.bits.source, r.size) io.in(i).d.bits.source := trim(in(i).d.bits.source, r.size) + + if (node.edgesIn(i).client.anySupportProbe && node.edgesOut.exists(_.manager.anySupportAcquireB)) { + in(i).c <> io.in(i).c + in(i).e <> io.in(i).e + io.in(i).b <> in(i).b + in(i).c.bits.source := io.in(i).c.bits.source | UInt(r.start) + io.in(i).b.bits.source := trim(in(i).b.bits.source, r.size) + } else { + in(i).c.valid := Bool(false) + in(i).e.valid := Bool(false) + in(i).b.ready := Bool(false) + io.in(i).c.ready := Bool(true) + io.in(i).e.ready := Bool(true) + io.in(i).b.valid := Bool(false) + } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io.out.size, TLBundle(wide_bundle))) for (i <- 0 until out.size) { val r = outputIdRanges(i) - io.out(i) <> out(i) - // prefix sinks + + io.out(i).a <> out(i).a + out(i).d <> io.out(i).d out(i).d.bits.sink := io.out(i).d.bits.sink | UInt(r.start) - // defix sinks - io.out(i).e.bits.sink := trim(out(i).e.bits.sink, r.size) + + if (node.edgesOut(i).manager.anySupportAcquireB && node.edgesIn.exists(_.client.anySupportProbe)) { + io.out(i).c <> out(i).c + io.out(i).e <> out(i).e + out(i).b <> io.out(i).b + io.out(i).e.bits.sink := trim(out(i).e.bits.sink, r.size) + } else { + out(i).c.ready := Bool(false) + out(i).e.ready := Bool(false) + out(i).b.valid := Bool(false) + io.out(i).c.valid := Bool(false) + io.out(i).e.valid := Bool(false) + io.out(i).b.ready := Bool(true) + } } val addressA = (in zip node.edgesIn) map { case (i, e) => e.address(i.a.bits) } From 0c92283a6112a72bf3997aebf226068753b4751a Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sun, 19 Mar 2017 17:18:50 -0700 Subject: [PATCH 3/3] rocket icache: tie off b ready --- src/main/scala/rocket/ICache.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index c56b3eb1..aebb4534 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -156,6 +156,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) fromSource = UInt(0), toAddress = (refill_addr >> blockOffBits) << blockOffBits, lgSize = lgCacheBlockBytes)._2 + tl_out.b.ready := Bool(true) tl_out.c.valid := Bool(false) tl_out.e.valid := Bool(false)