riscv/rocket-chip
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Bump Chisel and Firrtl (#1134)

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Jack Koenig 2017-12-08 14:22:18 -08:00 committed by GitHub
parent 9cc37b8444
commit 588dacec17
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 5 additions and 3 deletions
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2
chisel3

@ -1 +1 @@
Subproject commit e2c5c128f6509805f71aeca790809b3e9a8fe84d
Subproject commit 30e8eb552a29b22bc23faa06f5661da6129188b2

2
firrtl

@ -1 +1 @@
Subproject commit 5e23294dc6ac3c1937c9f071f970178c9f724037
Subproject commit 40dda493a277f721306d428ee967dcb670813275

2
src/main/scala/jtag/JtagStateMachine.scala
View File

@ -78,7 +78,7 @@ class JtagStateMachine(implicit val p: Parameters) extends Module(override_reset
}
val io = IO(new StateMachineIO)
val nextState = Wire(JtagState.State.chiselType())
val nextState = WireInit(JtagState.State.chiselType(), DontCare)
val currStateReg = Module (new AsyncResetRegVec(w = JtagState.State.width,
init = JtagState.State.toInt(JtagState.TestLogicReset)))

2
src/main/scala/jtag/JtagTap.scala
View File

@ -111,6 +111,7 @@ class JtagTapController(irLength: Int, initialInstruction: BigInt)(implicit val
nextActiveInstruction := irChain.io.update.bits
updateInstruction := true.B
} .otherwise {
nextActiveInstruction := DontCare
updateInstruction := false.B
}
io.output.instruction := activeInstruction
@ -135,6 +136,7 @@ class JtagTapController(irLength: Int, initialInstruction: BigInt)(implicit val
tdo := irChain.io.chainOut.data
tdo_driven := true.B
} .otherwise {
tdo := DontCare
tdo_driven := false.B
}
}