From 588dacec1778b4af14f9d1fb2f49dfa8ec5c2b5d Mon Sep 17 00:00:00 2001
From: Jack Koenig <jack.koenig3@gmail.com>
Date: Fri, 8 Dec 2017 14:22:18 -0800
Subject: [PATCH] Bump Chisel and Firrtl (#1134)

---
 chisel3                                    | 2 +-
 firrtl                                     | 2 +-
 src/main/scala/jtag/JtagStateMachine.scala | 2 +-
 src/main/scala/jtag/JtagTap.scala          | 2 ++
 4 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/chisel3 b/chisel3
index e2c5c128..30e8eb55 160000
--- a/chisel3
+++ b/chisel3
@@ -1 +1 @@
-Subproject commit e2c5c128f6509805f71aeca790809b3e9a8fe84d
+Subproject commit 30e8eb552a29b22bc23faa06f5661da6129188b2
diff --git a/firrtl b/firrtl
index 5e23294d..40dda493 160000
--- a/firrtl
+++ b/firrtl
@@ -1 +1 @@
-Subproject commit 5e23294dc6ac3c1937c9f071f970178c9f724037
+Subproject commit 40dda493a277f721306d428ee967dcb670813275
diff --git a/src/main/scala/jtag/JtagStateMachine.scala b/src/main/scala/jtag/JtagStateMachine.scala
index 91228d02..5e64b1e4 100644
--- a/src/main/scala/jtag/JtagStateMachine.scala
+++ b/src/main/scala/jtag/JtagStateMachine.scala
@@ -78,7 +78,7 @@ class JtagStateMachine(implicit val p: Parameters) extends Module(override_reset
   }
   val io = IO(new StateMachineIO)
 
-  val nextState = Wire(JtagState.State.chiselType())
+  val nextState = WireInit(JtagState.State.chiselType(), DontCare)
 
   val currStateReg = Module (new AsyncResetRegVec(w = JtagState.State.width,
     init = JtagState.State.toInt(JtagState.TestLogicReset)))
diff --git a/src/main/scala/jtag/JtagTap.scala b/src/main/scala/jtag/JtagTap.scala
index c935cd30..d97a6a33 100644
--- a/src/main/scala/jtag/JtagTap.scala
+++ b/src/main/scala/jtag/JtagTap.scala
@@ -111,6 +111,7 @@ class JtagTapController(irLength: Int, initialInstruction: BigInt)(implicit val
     nextActiveInstruction := irChain.io.update.bits
     updateInstruction := true.B
   } .otherwise {
+    nextActiveInstruction := DontCare
     updateInstruction := false.B
   }
   io.output.instruction := activeInstruction
@@ -135,6 +136,7 @@ class JtagTapController(irLength: Int, initialInstruction: BigInt)(implicit val
     tdo := irChain.io.chainOut.data
     tdo_driven := true.B
   } .otherwise {
+    tdo := DontCare
     tdo_driven := false.B
   }
 }