Bump Chisel and Firrtl (#1134)
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2
chisel3
2
chisel3
Submodule chisel3 updated: e2c5c128f6...30e8eb552a
2
firrtl
2
firrtl
Submodule firrtl updated: 5e23294dc6...40dda493a2
@ -78,7 +78,7 @@ class JtagStateMachine(implicit val p: Parameters) extends Module(override_reset
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}
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val io = IO(new StateMachineIO)
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val nextState = Wire(JtagState.State.chiselType())
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val nextState = WireInit(JtagState.State.chiselType(), DontCare)
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val currStateReg = Module (new AsyncResetRegVec(w = JtagState.State.width,
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init = JtagState.State.toInt(JtagState.TestLogicReset)))
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@ -111,6 +111,7 @@ class JtagTapController(irLength: Int, initialInstruction: BigInt)(implicit val
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nextActiveInstruction := irChain.io.update.bits
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updateInstruction := true.B
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} .otherwise {
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nextActiveInstruction := DontCare
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updateInstruction := false.B
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}
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io.output.instruction := activeInstruction
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@ -135,6 +136,7 @@ class JtagTapController(irLength: Int, initialInstruction: BigInt)(implicit val
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tdo := irChain.io.chainOut.data
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tdo_driven := true.B
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} .otherwise {
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tdo := DontCare
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tdo_driven := false.B
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}
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}
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