riscv/rocket-chip
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Bump Chisel and Firrtl (#1134)

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This commit is contained in:
Jack Koenig
2017-12-08 14:22:18 -08:00
committed by GitHub
parent 9cc37b8444
commit 588dacec17
4 changed files with 5 additions and 3 deletions
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2
chisel3

Submodule chisel3 updated: e2c5c128f6...30e8eb552a

2
firrtl

Submodule firrtl updated: 5e23294dc6...40dda493a2

2
src/main/scala/jtag/JtagStateMachine.scala
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@ -78,7 +78,7 @@ class JtagStateMachine(implicit val p: Parameters) extends Module(override_reset
} }
val io = IO(new StateMachineIO) val io = IO(new StateMachineIO)
val nextState = Wire(JtagState.State.chiselType()) val nextState = WireInit(JtagState.State.chiselType(), DontCare)
val currStateReg = Module (new AsyncResetRegVec(w = JtagState.State.width, val currStateReg = Module (new AsyncResetRegVec(w = JtagState.State.width,
init = JtagState.State.toInt(JtagState.TestLogicReset))) init = JtagState.State.toInt(JtagState.TestLogicReset)))

2
src/main/scala/jtag/JtagTap.scala
View File

@ -111,6 +111,7 @@ class JtagTapController(irLength: Int, initialInstruction: BigInt)(implicit val
nextActiveInstruction := irChain.io.update.bits nextActiveInstruction := irChain.io.update.bits
updateInstruction := true.B updateInstruction := true.B
} .otherwise { } .otherwise {
nextActiveInstruction := DontCare
updateInstruction := false.B updateInstruction := false.B
} }
io.output.instruction := activeInstruction io.output.instruction := activeInstruction
@ -135,6 +136,7 @@ class JtagTapController(irLength: Int, initialInstruction: BigInt)(implicit val
tdo := irChain.io.chainOut.data tdo := irChain.io.chainOut.data
tdo_driven := true.B tdo_driven := true.B
} .otherwise { } .otherwise {
tdo := DontCare
tdo_driven := false.B tdo_driven := false.B
} }
} }