riscv/rocket-chip
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sbus => pbus: 2 buffers should already be enough

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There is a buffer on the sbus backside.
There is a buffer on the pbus frontside.

Between them is only an AtomicAutomata.
That should be enough for most designs.
This commit is contained in:
Wesley W. Terpstra 2017-09-05 13:33:34 -07:00
parent a902e15987
commit 5886025b1a
2 changed files with 2 additions and 2 deletions
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2
src/main/scala/coreplex/PeripheryBus.scala
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@ -48,5 +48,5 @@ trait HasPeripheryBus extends HasSystemBus {
val pbus = new PeripheryBus(pbusParams)
// The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
pbus.fromSystemBus := sbus.toPeripheryBus(addBuffers = 1)
pbus.fromSystemBus := sbus.toPeripheryBus()
}

2
src/main/scala/coreplex/SystemBus.scala
View File

@ -37,7 +37,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
def toSplitSlaves: TLOutwardNode = outwardSplitNode
def toPeripheryBus(addBuffers: Int): TLOutwardNode = {
def toPeripheryBus(addBuffers: Int = 0): TLOutwardNode = {
val (in, out) = bufferChain(addBuffers, name = Some("pbus"))
in := pbus_fixer.node
out