From 5886025b1a2ec10c8bea501135dfc771d2ed277a Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 5 Sep 2017 13:33:34 -0700 Subject: [PATCH] sbus => pbus: 2 buffers should already be enough There is a buffer on the sbus backside. There is a buffer on the pbus frontside. Between them is only an AtomicAutomata. That should be enough for most designs. --- src/main/scala/coreplex/PeripheryBus.scala | 2 +- src/main/scala/coreplex/SystemBus.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/coreplex/PeripheryBus.scala b/src/main/scala/coreplex/PeripheryBus.scala index 7cbbdb56..04ec0338 100644 --- a/src/main/scala/coreplex/PeripheryBus.scala +++ b/src/main/scala/coreplex/PeripheryBus.scala @@ -48,5 +48,5 @@ trait HasPeripheryBus extends HasSystemBus { val pbus = new PeripheryBus(pbusParams) // The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL - pbus.fromSystemBus := sbus.toPeripheryBus(addBuffers = 1) + pbus.fromSystemBus := sbus.toPeripheryBus() } diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala index 35cfb1c6..6f0a371d 100644 --- a/src/main/scala/coreplex/SystemBus.scala +++ b/src/main/scala/coreplex/SystemBus.scala @@ -37,7 +37,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr def toSplitSlaves: TLOutwardNode = outwardSplitNode - def toPeripheryBus(addBuffers: Int): TLOutwardNode = { + def toPeripheryBus(addBuffers: Int = 0): TLOutwardNode = { val (in, out) = bufferChain(addBuffers, name = Some("pbus")) in := pbus_fixer.node out