sbus => pbus: 2 buffers should already be enough

There is a buffer on the sbus backside.
There is a buffer on the pbus frontside.

Between them is only an AtomicAutomata.
That should be enough for most designs.

src/main/scala/coreplex/PeripheryBus.scala

@@ -48,5 +48,5 @@ trait HasPeripheryBus extends HasSystemBus {
   val pbus = new PeripheryBus(pbusParams)
 
   // The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
-  pbus.fromSystemBus := sbus.toPeripheryBus(addBuffers = 1)
+  pbus.fromSystemBus := sbus.toPeripheryBus()
 }