From 5828e6042e831100b85df6bfaec184a9838965ff Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 14 Sep 2016 11:47:10 -0700 Subject: [PATCH] Work around https://github.com/ucb-bar/firrtl/issues/299 --- src/main/scala/junctions/hasti.scala | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/main/scala/junctions/hasti.scala b/src/main/scala/junctions/hasti.scala index 6063729e..9a36048f 100644 --- a/src/main/scala/junctions/hasti.scala +++ b/src/main/scala/junctions/hasti.scala @@ -521,10 +521,8 @@ class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p) // In case we are stalled, we need to hold the read data val d_rdata = holdUnless(mem.read(a_address, read), RegNext(read)) // Whenever the port is not needed for reading, execute pending writes - when (!read) { - when (p_valid) { mem.write(p_address, p_wdata, p_mask.toBools) } - p_valid := Bool(false) - } + when (!read && p_valid) { mem.write(p_address, p_wdata, p_mask.toBools) } + when (!read) { p_valid := Bool(false) } // Record the request for later? when (ready && a_request && a_write) {