riscv/rocket-chip
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first steps in uncore constant/tilelink data refactor

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This commit is contained in:
Henry Cook
2014-03-30 08:13:05 -07:00
parent d055c0ebaf 8d68ea9e0b 16274a84b6
commit 56f515c255
14 changed files with 225 additions and 234 deletions
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emulator/Makefile
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@@ -15,7 +15,7 @@ LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L. -ldramsim -lfes
OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL))
DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir emulator/generated-src
CHISEL_ARGS := $(MODEL) --noIoDebug --backend Chisel.Fame1CppBackend --targetDir emulator/generated-src
CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd --ioDebug
generated-src/$(MODEL).h: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala