From 6951333a084bb1386da9402a4ad27e85d58df520 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 4 Mar 2014 23:43:00 -0800 Subject: [PATCH 01/10] push rocket --- rocket | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket b/rocket index 49f633cd..004dc6f5 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 49f633cd12de6e69479943d8089563edae7e03f5 +Subproject commit 004dc6f502d88f83580261bfbd88d2e3ebd727c8 From f04bde75fb88d9aabac7f713856efb6df9a50a69 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 11 Mar 2014 19:12:20 -0700 Subject: [PATCH 02/10] New FP encoding --- Makefrag | 2 ++ chisel | 2 +- riscv-tools | 2 +- rocket | 2 +- 4 files changed, 5 insertions(+), 3 deletions(-) diff --git a/Makefrag b/Makefrag index 0ef0653c..497b04b2 100644 --- a/Makefrag +++ b/Makefrag @@ -109,6 +109,7 @@ asm_p_tests = \ rv64uf-p-fcmp \ rv64uf-p-fcvt \ rv64uf-p-fcvt_w \ + rv64uf-p-fclass \ rv64uf-p-fadd \ rv64uf-p-fmin \ rv64uf-p-fmadd \ @@ -205,6 +206,7 @@ asm_v_tests = \ rv64uf-v-fcmp \ rv64uf-v-fcvt \ rv64uf-v-fcvt_w \ + rv64uf-v-fclass \ rv64uf-v-fadd \ rv64uf-v-fmin \ rv64uf-v-fmadd \ diff --git a/chisel b/chisel index 25a33ba1..9ceee822 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 25a33ba1d456294fe4ebc79fe95339a0d9d20e8a +Subproject commit 9ceee82282839f0dd2d11eb13b59b0a9245944cc diff --git a/riscv-tools b/riscv-tools index ebb909ab..85dad284 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit ebb909ab9dfff8387449faa5827d47eda693b70b +Subproject commit 85dad28489c39eb0ea2bc4ef3dc86b9fd8f75ca5 diff --git a/rocket b/rocket index 004dc6f5..76b583c8 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 004dc6f502d88f83580261bfbd88d2e3ebd727c8 +Subproject commit 76b583c8f3d279c4c9f0eea0947df25dec2ef5fb From 7ac003a4f754042f03d9f16c85223a5d4fbed238 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 11 Mar 2014 20:36:39 -0700 Subject: [PATCH 03/10] push hardfloat --- hardfloat | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hardfloat b/hardfloat index 39a08130..2a05ecbb 160000 --- a/hardfloat +++ b/hardfloat @@ -1 +1 @@ -Subproject commit 39a08130d41ceb9e7f98fa7092fc38970009a460 +Subproject commit 2a05ecbb351304464cfedd02890dafb80bfad6d7 From b6bf7cfe0caaf9b00dca586a76597d0e8f88dac7 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 11 Mar 2014 23:56:57 -0700 Subject: [PATCH 04/10] push chisel --- chisel | 2 +- riscv-tools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/chisel b/chisel index 9ceee822..ada8369a 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 9ceee82282839f0dd2d11eb13b59b0a9245944cc +Subproject commit ada8369a39e82890cd78b04db6661f426fb57df2 diff --git a/riscv-tools b/riscv-tools index 85dad284..bc6bbf50 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 85dad28489c39eb0ea2bc4ef3dc86b9fd8f75ca5 +Subproject commit bc6bbf5024bc5297a928b8620ad0364e44d26cfe From e4b56b5d0e2320ac7d2261d0fe60ec1d9fdf09fd Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 15 Mar 2014 15:31:04 -0700 Subject: [PATCH 05/10] generate verilog for rekall --- project/build.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/project/build.scala b/project/build.scala index a6f98650..877c66a4 100644 --- a/project/build.scala +++ b/project/build.scala @@ -31,7 +31,8 @@ object BuildSettings extends Build { lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(hardfloat) lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore) lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(uncore, rocket) - lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha) + lazy val rekall = Project("rekall", file("rekall"), settings = buildSettings) dependsOn(chisel) + lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha, rekall) val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code") val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command") From 7f23257873c8a62c93e4447876457a5772010362 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 17 Mar 2014 15:35:17 -0700 Subject: [PATCH 06/10] Print out random seed if test fails --- csrc/emulator.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/csrc/emulator.cc b/csrc/emulator.cc index 6b90d469..f7d73aaa 100644 --- a/csrc/emulator.cc +++ b/csrc/emulator.cc @@ -139,7 +139,7 @@ int main(int argc, char** argv) if (htif->exit_code()) { - fprintf(stderr, "*** FAILED *** (code = %d) after %lld cycles\n", htif->exit_code(), (long long)trace_count); + fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %lld cycles\n", htif->exit_code(), random_seed, (long long)trace_count); ret = htif->exit_code(); } else if (trace_count == max_cycles) From 0d124d283a8850061e8e738eddcc67dbb9ee1c73 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 17 Mar 2014 17:02:28 -0700 Subject: [PATCH 07/10] Write our own vcs main() routine --- chisel | 2 +- csrc/vcs_main.cc | 82 ++++++++++++++++++++++-------------------------- 2 files changed, 38 insertions(+), 46 deletions(-) diff --git a/chisel b/chisel index f8c3c094..a2388fee 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit f8c3c094a685c1f5630bd2f61ba0434c2dfbd58f +Subproject commit a2388fee713e67b5b4f490ae203093dd8d9a5d33 diff --git a/csrc/vcs_main.cc b/csrc/vcs_main.cc index a406a826..9efcd6fb 100644 --- a/csrc/vcs_main.cc +++ b/csrc/vcs_main.cc @@ -8,12 +8,41 @@ #include #include -static htif_emulator_t* htif = NULL; -static unsigned htif_bytes; -static mm_t* mm = NULL; - extern "C" { +extern int vcs_main(int argc, char** argv); + +static htif_emulator_t* htif; +static unsigned htif_bytes; +static mm_t* mm; +static const char* loadmem; + +void htif_fini(int code) +{ + delete htif; + htif = NULL; + exit(code); +} + +int main(int argc, char** argv) +{ + bool dramsim = false; + + for (int i = 1; i < argc; i++) + { + if (!strcmp(argv[i], "+dramsim")) + dramsim = true; + else if (!strncmp(argv[i], "+loadmem=", 9)) + loadmem = argv[i]+9; + } + + mm = dramsim ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t); + htif = new htif_emulator_t(std::vector(argv + 1, argv + argc)); + + vcs_main(argc, argv); + abort(); // should never get here +} + void memory_tick( vc_handle mem_req_val, vc_handle mem_req_rdy, @@ -62,55 +91,18 @@ void memory_tick( ); } -void htif_init -( - vc_handle htif_width, - vc_handle mem_width, - vc_handle argv, - vc_handle loadmem, - vc_handle dramsim -) +void htif_init(vc_handle htif_width, vc_handle mem_width) { int mw = vc_4stVectorRef(mem_width)->d; - mm = vc_getScalar(dramsim) ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t); assert(mw && (mw & (mw-1)) == 0); mm->init(MEM_SIZE, mw/8, LINE_SIZE); + if (loadmem) + load_mem(mm->get_data(), loadmem); + vec32* w = vc_4stVectorRef(htif_width); assert(w->d <= 32 && w->d % 8 == 0); // htif_tick assumes data fits in a vec32 htif_bytes = w->d/8; - - char loadmem_str[1024]; - vc_VectorToString(loadmem, loadmem_str); - if (*loadmem_str) - load_mem(mm->get_data(), loadmem_str); - - char argv_str[1024]; - vc_VectorToString(argv, argv_str); - if (!*argv_str) - { - if (*loadmem_str) - strcpy(argv_str, "none"); - else - { - fprintf(stderr, "Usage: ./simv [host options] +argv=\" [target args]\"\n"); - exit(-1); - } - } - - std::vector args; - std::stringstream ss(argv_str); - std::istream_iterator begin(ss), end; - std::copy(begin, end, std::back_inserter>(args)); - - htif = new htif_emulator_t(args); -} - -void htif_fini(vc_handle failure) -{ - delete htif; - htif = NULL; - exit(vc_getScalar(failure)); } void htif_tick From d2c32b048a2facb667e24962b1f8549315d3f777 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 18 Mar 2014 01:35:08 -0700 Subject: [PATCH 08/10] fix bug in htif_fini, need to use vc_handle! --- csrc/vcs_main.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/csrc/vcs_main.cc b/csrc/vcs_main.cc index 9efcd6fb..cc9e4a06 100644 --- a/csrc/vcs_main.cc +++ b/csrc/vcs_main.cc @@ -17,11 +17,11 @@ static unsigned htif_bytes; static mm_t* mm; static const char* loadmem; -void htif_fini(int code) +void htif_fini(vc_handle failure) { delete htif; htif = NULL; - exit(code); + exit(vc_getScalar(failure)); } int main(int argc, char** argv) From 51808d998257cef9a82d00b45dd2c8c908a18acf Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 18 Mar 2014 18:37:53 -0700 Subject: [PATCH 09/10] Fix minor FP bugs --- hardfloat | 2 +- riscv-tests | 2 +- rocket | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hardfloat b/hardfloat index 2a05ecbb..8415eba0 160000 --- a/hardfloat +++ b/hardfloat @@ -1 +1 @@ -Subproject commit 2a05ecbb351304464cfedd02890dafb80bfad6d7 +Subproject commit 8415eba06ffac9dfa5203bfca9b10afae2316961 diff --git a/riscv-tests b/riscv-tests index ea6edc71..7e146003 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit ea6edc71edb84d9eb9241decd04ee3374a895f0c +Subproject commit 7e1460032cf6f522ce4bc7e8a347c1f08a4476d2 diff --git a/rocket b/rocket index ddb2db3f..09f42649 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit ddb2db3f69ffabf9c985f76614603b4b0265c815 +Subproject commit 09f426491ec357cdffee10071a4e3c3b8ba779b3 From 16274a84b6afde352a4f9eadcffb32d12a1c5120 Mon Sep 17 00:00:00 2001 From: Donggyu Kim Date: Fri, 21 Mar 2014 16:21:15 -0700 Subject: [PATCH 10/10] update fpga testbench --- chisel | 2 +- hardfloat | 2 +- riscv-tests | 2 +- rocket | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/chisel b/chisel index d151bbef..2f678db2 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit d151bbeff7bd9917415257482e26760d5fdc1166 +Subproject commit 2f678db2c9013b9a6b6e305784b17997d630517a diff --git a/hardfloat b/hardfloat index 8415eba0..2a05ecbb 160000 --- a/hardfloat +++ b/hardfloat @@ -1 +1 @@ -Subproject commit 8415eba06ffac9dfa5203bfca9b10afae2316961 +Subproject commit 2a05ecbb351304464cfedd02890dafb80bfad6d7 diff --git a/riscv-tests b/riscv-tests index 7e146003..ea6edc71 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit 7e1460032cf6f522ce4bc7e8a347c1f08a4476d2 +Subproject commit ea6edc71edb84d9eb9241decd04ee3374a895f0c diff --git a/rocket b/rocket index 489d3b1c..ddb2db3f 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 489d3b1cd57bbdcf443247a359214b644c5c1e9f +Subproject commit ddb2db3f69ffabf9c985f76614603b4b0265c815