From 56897f707ab972c5724d6168836fb8ea28e8489f Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 27 May 2016 12:23:39 -0700 Subject: [PATCH] Don't rely on Mux1H output when no inputs are hot --- junctions/src/main/scala/hasti.scala | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/junctions/src/main/scala/hasti.scala b/junctions/src/main/scala/hasti.scala index a193bbd1..550e3a42 100644 --- a/junctions/src/main/scala/hasti.scala +++ b/junctions/src/main/scala/hasti.scala @@ -272,20 +272,23 @@ class HastiXbar(nMasters: Int, addressMap: Seq[UInt=>Bool])(implicit p: Paramete diversions(m).io.divert := bubbleM(m) && NSeq(m) && masters(m).hready } + def dotProduct(g: Seq[Bool], v: Seq[UInt]) = + (g zip v) map { case (gg, ss) => Mux(gg, ss, ss.fromBits(UInt(0))) } reduce (_|_) + // Master muxes (address and data phase are the same) (masters zip (unionGrantMS zip nowhereM)) foreach { case (m, (g, n)) => { // If the master is connected to a slave, the slave determines hready. // However, if no slave is connected, for progress report ready anyway, if: // bad address (swallow request) OR idle (permit stupid slaves to move FSM) val autoready = n || m.isIdle() - m.hready := Mux1H(g, slaves.map(_.hready ^ autoready)) ^ autoready + m.hready := dotProduct(g, slaves.map(_.hready ^ autoready)) ^ autoready m.hrdata := Mux1H(g, slaves.map(_.hrdata)) m.hresp := Mux1H(g, slaves.map(_.hresp)) } } // Slave address phase muxes (slaves zip addressPhaseGrantSM) foreach { case (s, g) => { - s.htrans := Mux1H(g, masters.map(_.htrans)) // defaults to HTRANS_IDLE (0) + s.htrans := dotProduct(g, masters.map(_.htrans)) // defaults to HTRANS_IDLE (0) s.haddr := Mux1H(g, masters.map(_.haddr)) s.hmastlock := isLocked s.hwrite := Mux1H(g, masters.map(_.hwrite))