From 560fdc19a882ac625f75dd80fcc9026d1c69bdeb Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Wed, 16 Dec 2015 10:24:57 -0800
Subject: [PATCH] add PLRU replacement option to L2 cache

---
 src/main/scala/Configs.scala | 8 ++++++++
 uncore                       | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index f47b21a8..f9f1847a 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -261,10 +261,16 @@ class WithL2Cache extends Config(
         case CacheName => "L2Bank"
         case InnerTLId => "L1toL2"
         case OuterTLId => "L2toMC"})))
+    case L2Replacer => () => new SeqRandom(site(NWays))
   },
   knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048 }
 )
 
+class WithPLRU extends Config(
+  (pname, site, here) => pname match {
+    case L2Replacer => () => new SeqPLRU(site(NSets), site(NWays))
+  })
+
 class WithL2Capacity2048 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 2048 })
 class WithL2Capacity1024 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 1024 })
 class WithL2Capacity512 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 512 })
@@ -281,6 +287,8 @@ class DefaultL2VLSIConfig extends Config(new WithL2Cache ++ new DefaultVLSIConfi
 class DefaultL2CPPConfig extends Config(new WithL2Cache ++ new DefaultCPPConfig)
 class DefaultL2FPGAConfig extends Config(new WithL2Capacity64 ++ new WithL2Cache ++ new DefaultFPGAConfig)
 
+class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
+
 class WithZscale extends Config(
   (pname,site,here) => pname match {
     case XLen => 32
diff --git a/uncore b/uncore
index ab8a6614..f9eda0eb 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit ab8a6614f5495ee97c5b8bb82047ebb24cb20d7c
+Subproject commit f9eda0ebb010a4bf99609d2ef6f93b85756e3ccb