riscv/rocket-chip
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Added jack Makefile and hammer.scala, as well as changed reference chip to have multiple datacache sizes. Requires chisel branch dse

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This commit is contained in:
Adam Izraelevitz
2014-02-11 14:36:47 -08:00
parent 7c11cf49b8
commit 548cf16061
4 changed files with 12 additions and 4 deletions
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5
Makefrag
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@@ -14,6 +14,11 @@ $(sim_dir)/libdramsim.a: $(DRAMSIM_OBJS)
src_path = src/main/scala src_path = src/main/scala
#DESIGN := design_dsize8_c20b273
SRC := rocket/$(src_path)/*.scala hwacha/$(src_path)/*.scala /uncore/$(src_path)/*.scala $(src_path)/*.scala
PROJ := referencechip
#-------------------------------------------------------------------- #--------------------------------------------------------------------
# Tests # Tests
#-------------------------------------------------------------------- #--------------------------------------------------------------------

2
chisel

Submodule chisel updated: ae1d1de821...fcb94b3e4a

2
riscv-tests

Submodule riscv-tests updated: a481561500...0c98ef833d

7
src/main/scala/RocketChip.scala
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@@ -252,8 +252,11 @@ class Top extends Module {
implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64) implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64)
val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 38) val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 38)
val dc = DCacheConfig(128, 4, ntlb = 8,
nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates) val dsize = RangeParam("dsize",7,7,9)
val dc = DCacheConfig(math.pow(2, dsize.getValue).toInt, 4, ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
//val dc = DCacheConfig(128, 4, ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
val rc = RocketConfiguration(tl, ic, dc, val rc = RocketConfiguration(tl, ic, dc,
fpu = HAS_FPU) fpu = HAS_FPU)