diff --git a/Makefrag b/Makefrag
index 7c92290f..beb8126b 100644
--- a/Makefrag
+++ b/Makefrag
@@ -14,6 +14,11 @@ $(sim_dir)/libdramsim.a: $(DRAMSIM_OBJS)
 
 src_path = src/main/scala
 
+#DESIGN := design_dsize8_c20b273
+SRC := rocket/$(src_path)/*.scala hwacha/$(src_path)/*.scala /uncore/$(src_path)/*.scala $(src_path)/*.scala
+PROJ := referencechip
+
+
 #--------------------------------------------------------------------
 # Tests
 #--------------------------------------------------------------------
diff --git a/chisel b/chisel
index ae1d1de8..fcb94b3e 160000
--- a/chisel
+++ b/chisel
@@ -1 +1 @@
-Subproject commit ae1d1de82188f0a1d79a4e8eb613743942a13eb3
+Subproject commit fcb94b3e4acdc005935f6af91a768a7ff96d971c
diff --git a/riscv-tests b/riscv-tests
index a4815615..0c98ef83 160000
--- a/riscv-tests
+++ b/riscv-tests
@@ -1 +1 @@
-Subproject commit a481561500f43c8a022cfc0ba1695914e1df4d57
+Subproject commit 0c98ef833db1f6eead3bd9ad083d9408d2d8decb
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index deb400f7..2c7996cc 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -252,8 +252,11 @@ class Top extends Module {
   implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64)
 
   val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 38)
-  val dc = DCacheConfig(128, 4, ntlb = 8, 
-                        nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
+
+  val dsize = RangeParam("dsize",7,7,9)
+  val dc = DCacheConfig(math.pow(2, dsize.getValue).toInt, 4, ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
+  //val dc = DCacheConfig(128, 4, ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
+
   val rc = RocketConfiguration(tl, ic, dc,
                                fpu = HAS_FPU)