riscv/rocket-chip
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periphery: use SimpleBus for mmio ports

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This commit is contained in:
Wesley W. Terpstra 2017-06-28 13:58:06 -07:00
parent 171e1a4c05
commit 5436be54ff
1 changed files with 4 additions and 4 deletions
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8
src/main/scala/rocketchip/Periphery.scala
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@ -177,11 +177,11 @@ trait HasPeripheryMasterAXI4MemPortModuleImp extends LazyMultiIOModuleImp with H
/** Adds a AXI4 port to the system intended to master an MMIO device bus */ /** Adds a AXI4 port to the system intended to master an MMIO device bus */
trait HasPeripheryMasterAXI4MMIOPort extends HasSystemNetworks { trait HasPeripheryMasterAXI4MMIOPort extends HasSystemNetworks {
private val config = p(ExtBus) private val config = p(ExtBus)
private val device = new SimpleDevice("mmio", Nil) private val device = new SimpleBus("mmio", Nil)
val mmio_axi4 = AXI4BlindOutputNode(Seq(AXI4SlavePortParameters( val mmio_axi4 = AXI4BlindOutputNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters( slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(BigInt(config.base), config.size-1)), address = List(AddressSet(BigInt(config.base), config.size-1)),
resources = device.reg, resources = device.ranges,
executable = true, // Can we run programs on this memory? executable = true, // Can we run programs on this memory?
supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
supportsRead = TransferSizes(1, 256))), supportsRead = TransferSizes(1, 256))),
@ -252,11 +252,11 @@ trait HasPeripherySlaveAXI4PortModuleImp extends LazyMultiIOModuleImp with HasPe
/** Adds a TileLink port to the system intended to master an MMIO device bus */ /** Adds a TileLink port to the system intended to master an MMIO device bus */
trait HasPeripheryMasterTLMMIOPort extends HasSystemNetworks { trait HasPeripheryMasterTLMMIOPort extends HasSystemNetworks {
private val config = p(ExtBus) private val config = p(ExtBus)
private val device = new SimpleDevice("mmio", Nil) private val device = new SimpleBus("mmio", Nil)
val mmio_tl = TLBlindOutputNode(Seq(TLManagerPortParameters( val mmio_tl = TLBlindOutputNode(Seq(TLManagerPortParameters(
managers = Seq(TLManagerParameters( managers = Seq(TLManagerParameters(
address = List(AddressSet(BigInt(config.base), config.size-1)), address = List(AddressSet(BigInt(config.base), config.size-1)),
resources = device.reg, resources = device.ranges,
executable = true, executable = true,
supportsGet = TransferSizes(1, cacheBlockBytes), supportsGet = TransferSizes(1, cacheBlockBytes),
supportsPutFull = TransferSizes(1, cacheBlockBytes), supportsPutFull = TransferSizes(1, cacheBlockBytes),