From 5436be54fff646b69c3e3248e937f0df51ad72f8 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 28 Jun 2017 13:58:06 -0700 Subject: [PATCH] periphery: use SimpleBus for mmio ports --- src/main/scala/rocketchip/Periphery.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala index fa817d5e..85a34ac4 100644 --- a/src/main/scala/rocketchip/Periphery.scala +++ b/src/main/scala/rocketchip/Periphery.scala @@ -177,11 +177,11 @@ trait HasPeripheryMasterAXI4MemPortModuleImp extends LazyMultiIOModuleImp with H /** Adds a AXI4 port to the system intended to master an MMIO device bus */ trait HasPeripheryMasterAXI4MMIOPort extends HasSystemNetworks { private val config = p(ExtBus) - private val device = new SimpleDevice("mmio", Nil) + private val device = new SimpleBus("mmio", Nil) val mmio_axi4 = AXI4BlindOutputNode(Seq(AXI4SlavePortParameters( slaves = Seq(AXI4SlaveParameters( address = List(AddressSet(BigInt(config.base), config.size-1)), - resources = device.reg, + resources = device.ranges, executable = true, // Can we run programs on this memory? supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers supportsRead = TransferSizes(1, 256))), @@ -252,11 +252,11 @@ trait HasPeripherySlaveAXI4PortModuleImp extends LazyMultiIOModuleImp with HasPe /** Adds a TileLink port to the system intended to master an MMIO device bus */ trait HasPeripheryMasterTLMMIOPort extends HasSystemNetworks { private val config = p(ExtBus) - private val device = new SimpleDevice("mmio", Nil) + private val device = new SimpleBus("mmio", Nil) val mmio_tl = TLBlindOutputNode(Seq(TLManagerPortParameters( managers = Seq(TLManagerParameters( address = List(AddressSet(BigInt(config.base), config.size-1)), - resources = device.reg, + resources = device.ranges, executable = true, supportsGet = TransferSizes(1, cacheBlockBytes), supportsPutFull = TransferSizes(1, cacheBlockBytes),