diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala
index fa817d5e..85a34ac4 100644
--- a/src/main/scala/rocketchip/Periphery.scala
+++ b/src/main/scala/rocketchip/Periphery.scala
@@ -177,11 +177,11 @@ trait HasPeripheryMasterAXI4MemPortModuleImp extends LazyMultiIOModuleImp with H
 /** Adds a AXI4 port to the system intended to master an MMIO device bus */
 trait HasPeripheryMasterAXI4MMIOPort extends HasSystemNetworks {
   private val config = p(ExtBus)
-  private val device = new SimpleDevice("mmio", Nil)
+  private val device = new SimpleBus("mmio", Nil)
   val mmio_axi4 = AXI4BlindOutputNode(Seq(AXI4SlavePortParameters(
     slaves = Seq(AXI4SlaveParameters(
       address       = List(AddressSet(BigInt(config.base), config.size-1)),
-      resources     = device.reg,
+      resources     = device.ranges,
       executable    = true,                  // Can we run programs on this memory?
       supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
       supportsRead  = TransferSizes(1, 256))),
@@ -252,11 +252,11 @@ trait HasPeripherySlaveAXI4PortModuleImp extends LazyMultiIOModuleImp with HasPe
 /** Adds a TileLink port to the system intended to master an MMIO device bus */
 trait HasPeripheryMasterTLMMIOPort extends HasSystemNetworks {
   private val config = p(ExtBus)
-  private val device = new SimpleDevice("mmio", Nil)
+  private val device = new SimpleBus("mmio", Nil)
   val mmio_tl = TLBlindOutputNode(Seq(TLManagerPortParameters(
     managers = Seq(TLManagerParameters(
       address            = List(AddressSet(BigInt(config.base), config.size-1)),
-      resources          = device.reg,
+      resources          = device.ranges,
       executable         = true,
       supportsGet        = TransferSizes(1, cacheBlockBytes),
       supportsPutFull    = TransferSizes(1, cacheBlockBytes),